M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 224

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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Table 14.1.8.1 Delayed Trigger Mode 1 Specifications
0
NOTES:
C
14.1.8 Delayed Trigger Mode 1
2
9
A/D Conversion Start
Readout of A/D Conversion Result
0 .
2 /
Function
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Analog Input Pin
B
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the AD
conversion is started. After completing the AN
until the second AD
The single sweep conversion of the pins after the AN
trigger mode 1 specifications. Figure 14.1.8.1 shows the operation example of delayed trigger mode 1.
Figure 14.1.8.2 to Figure 14.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 14.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger
mode 1. Figure 14.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2
shows the trigger select bit setting in delayed trigger mode 1.
0
1. Do not generate the next AD
2. The AD
3. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write “1”, unexpected
4. AN
0
6
2
A
complete A/D conversion. When an AD
is ignored. The falling edge of AD
considered to be the next AN0 pin conversion start condition.
falling edge is generated in shorter periods than
not generate the AD
interrupts may be generated.
group.
0
F
2
e
G
0 -
b
30
Item
o r
1 .
___________
2
0
to AN
u
, 5
0
p
TRG
2
(
0
M
0
32
pin falling edge is detected synchronized with the operation clock
7
1
6
can be used in the same way as AN
C
page 205
2 /
___________
TRG
6
TRG
, A
pin falling edge is generated. When the second AD
M
pin falling edge in shorter periods than
1
___________
f o
6
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltages applied to the selected pins are
converted one-by-one to a digital code. At this time, the AD
falling edge starts AN
conversion of the pins after AN
AN
AN
Single sweep conversion completed
Select from AN
AN
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
The AD
The AD
C
3
•When the second AD
•When the AD
•A/D conversion completed
•Set the ADST bit to "0" (A/D conversion halted)
TRG
falling edge. The conversion of AN
conversion is completed.
conversion of the AN
2
2 /
0
1
sion of pins after the AN
0
___________
9
pin conversion start condition
pin conversion start condition
to AN
6
, B
pin falling edge after the AN1 pin conversion is started until all selected pins
TRG
TRG
___________
TRG
M
7
TRG
pin, which was input after all selected pins complete A/D conversion, is
1
TRG
(8 pins)
pin input changes state from “H” to “L” (falling edge)
6
pin input changes state from “H” to “L” (falling edge)
C
0
pin (falling edge) changes state from “H” to “L”, a single sweep
TRG
2 /
pin falling edge is generated again during A/D conversion, its trigger
to AN
6
0
(4)
) T
pin falling edge is generated again during single sweep conver
pin conversion, the AN
0
AD
1
pin conversion and the second AD
0
0
, the second AD
TRG
(2 pins), AN
pin, input voltage of AN
to AN
1
1
Specification
pin falling edge is generated during or after A/D
pin, the conversion is not affected
pin is restarted. Table 14.1.8.1 shows the delayed
7
1
. However, all input pins need to belong to the same
pin
(2)
0
___________
1
AD
to AN
and the rest of the sweep starts when AN
TRG
.
3
pin falling edge may not be detected. Do
(4 pins), AN
1
1
pin is not sampled and converted
pin is sampled at the time of AD
AD
TRG
. Therefore, when the AD
(3)
falling edge is generated,
0
TRG
to AN
TRG
pin falling edge starts
pin
5
(1)
(6 pins) and
14. A/D Converter
___________
TRG
0
TRG
pin