M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 349

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Rev.
2.00 Feb.15,07
REVISION HISTORY
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
M16C/26B newly added, word standardized: on-chip oscillator, development tool
Overview
•Description partially deleted
•1.2 Performance Outline modified
•Figure 1.1 and 1.2 Block Diagrams updated
•1.4 Product List updated
•Figure 1.3 Product Numbering System updated
•Tables 1.7 to 1.10 Product Codes updated
•Tables 1.11 and 1.12 Pin Characteristics newly added
•Tables 1.13 Pin Description newly added
SFRs
•Table 4.1 SFR Information(1) Note about WDC register is deleted
•Table 4.3 SFR Information(3) Value after reset for ROCR register modified
•Table 4.4 SFR Information(4) Note 2 added to IFSR2A register
Reset
•Figure 5.1.1.2. Reset Sequence Vcc line and ROC line are modified
•Figure 5.5.1. Voltage Detection Circuit Block WDC register’s block is deleted
Processor Mode
•Figure 6.1 PM1 Register Note 2 partially added
•Figure 6.2 PM2 Register newly added
•Figure 6.3 Bus Block Diagram and Table 6.1 Accessible Area and Bus Cycle
Clock Generation Circuit
•Figure 7.4 ROCR Register modified
•Figure 7.6 PM2 Register Notes 2, 5, 6 modified
•Figure 7.1.1 and 7.2.1 Examples of Main Clock Connection Circuit updated
•7.4 PLL Clock Description modified for M16C/26B
•Table 7.4.1 Example for Setting PLL Clock Frequencies Note 1 modified
•7.6.1 Normal Operation Mode Description modified
•Table 7.6.1.1 Setting Clock Related Bit and Modes modified
•Figure 7.6.1 State Transition to Stop Mode and Wait Mode modified
•Figure 7.6.1.1. State Transtion in Normal Mode modified
•Table 7.6.1 Allowed Transition and Setting modified, Notes 1 and 2 modified
•Figure 7.8.3.1 Procedure to Switch Clock Source From On-chip Oscillator
Protection
•Description partially modified
Interrupt
•9.6 INT Interrupt Description partially added
newly added
to Main Clock upadated
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C-1
Description
Summary