M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 324

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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Figure 19.2. Procedure for Changing the Interrupt Generate Factor
0
C
19.5.5 INT Interrupt
2
9
0 .
2 /
B
1. Either an “L” level of at least t
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
3. When using the INT
0
0
6
input to pins INT
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
debounce filter) before entering stop mode.
2
A
0
F
2
e
G
0 -
b
______
o r
1 .
2
0
u
, 5
0
p
NOTES:
2
(
0
M
1. The above settings must be executed individually. Do not execute two or more settings simultaneously
2. Use the I flag for the INTi interrupt (i = 0 to 5).
3. Refer to 19.5.6 Rewrite the Interrupt Control Register for details about the instructions to use and the
0
7
1
(using one instruction).
is the source of the interrupt in order not to generate an interrupt request before changing the interrupt
generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use
the I flag. Otherwise, use the corresponding
notes to be taken for instruction execution.
For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that
_______
6
C
page 305
0
2 /
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
Change the interrupt generate factor (including a mode change of peripheral function)
through INT
6
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3)
, A
5
interrupt for exiting stop mode, set the P17DDR register to “FF
M
be changed
1
f o
6
_______
C
3
2
2 /
9
5
W
6
regardless of the CPU operation clock.
(
, B
INH
M
) or an “H” level of at least t
1
6
Disable interrupts (2, 3)
C
Enable interrupts (2, 3)
Changing the interrupt source
2 /
6
) T
End of change
W
(
INL
) width is necessary for the signal
16
” (disable digital
19. Usage Notes