M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 74

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R
R
M
e
E
. v
J
1
0
Figure 7.6.1.1. State Transition in Normal Mode
6
2
9
C
0 .
B
2 /
0
0
2
6
0
F
A
2
e
NOTES:
Main clock oscillation
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
0 -
b
G
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
2. Wait for the main clock oscillation stabilization time before switching over. Set the CM15 bit in the CM1 register to 1 (drive capacity High) until main clock oscillation is stabilized.
3. Switch clock after oscillation of sub-clock is sufficiently stable.
4. Change bits CM17 and CM16 before changing the CM06 bit.
5. The PM20 bit in the PM2 register becomes effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off).
6. Set the CM06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
7. When the CM21 bit is set to 0 (on-chip oscillator turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the
1 .
2
o r
Sub clock oscillation
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
CM15 bit is fixed to 1 (drive capability High).
CPU clock: f(PLL)
PLL operation mode
0
, 5
CM04=1
CPU clock: f(PLL)
PLL operation
mode
0
u
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=0
2
p
0
(
0
M
7
1
CM04=0
6
C
page 55
PLC07=0
PLC07=0
PLC07=1
(5)
PLC07=1
(5)
(5)
CM11=1
CM11=0
CM11=0
2 /
CM11=1
(5)
6
, A
High-speed mode
M
High-speed mode
CPU clock: f(X
CPU clock: f(X
f o
1
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=0
6
3
C
2
IN
IN
)
)
2 /
9
6
CPU clock: f(X
Middle-speed mode
Middle-speed mode
CPU clock: f(X
, B
(divide by 2)
(divide by 2)
CM07=0
CM06=0
CM17=0
CM16=1
CM07=0
CM06=0
CM17=0
CM16=1
M
CM04=1
CM07=1
CM05=1
(1, 7)
(3)
IN
IN
)/2
)/2
1
6
Low power dissipation mode
C
Middle-speed mode
Middle-speed mode
CPU clock: f(X
CPU clock: f(X
CPU clock: f(X
CPU clock: f(X
Low-speed mode
(divide by 4)
(divide by 4)
2 /
CM07=0
CM06=0
CM17=1
CM16=0
CM07=0
CM06=0
CM17=1
CM16=0
CM07=0
CM07=0
CM06=1
CM15=1
6
) T
IN
IN
)/4
)/4
CIN
CIN
)
)
CPU clock: f(X
Middle-speed mode
Middle-speed mode
CPU clock: f(X
(divide by 8)
(divide by 8)
CM07=0
CM06=1
CM07=0
CM06=1
(2, 4)
CM04=0
CM07=0
CM05=0
IN
IN
)/8
)/8
Middle-speed mode
Middle-speed mode
CPU clock: f(X
CPU clock: f(X
(divide by 16)
(divide by 16)
CM07=0
CM06=0
CM17=1
CM16=1
CM07=0
CM06=0
CM17=1
CM16=1
IN
CM21=0
CM21=1
IN
)/16
)/16
CM21=0
CM21=1
CM21=0
CM21=1
(2, 6)
(2, 6)
CM07=1
(3)
On-chip oscillator mode
CPU clock: f(X
On-chip oscillator
mode
CM04=1
Low-speed
mode
CPU clock
CPU clock
CM07=0
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
CIN
7. Clock Generation Circuit
)
CM07=0
(4)
CM04=0
CM05=0
CM05=1
CM05=0
CM05=1
(1)
M0
M
(1)
On-chip oscillator clock
oscillation
On-chip oscillator low power
dissipation mode
CM04=1
On-chip oscillator
low power
dissipation mode
CPU clock
CPU clock
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
CM04=0