DF2166VT33V Renesas Electronics America, DF2166VT33V Datasheet - Page 32

• Manufacturer Part Number: DF2166VT33V
• Description: IC H8S MCU FLASH 512K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Package: 144TQFP
• Family Name: H8S
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 106
• Number Of Timers: 5
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: DF2166VTE33V; DF2166VTE33V; HD64F2166VTE33V; HD64F2166VTE33V

Figure 14.47 MSB-First Data Transmission............................................................................... 430
Figure 14.48 LSB-First Data Reception ..................................................................................... 431
Figure 14.49 MSB-First Data Reception .................................................................................... 432
Figure 14.50 LSB-First and MSB-First Transmit Data .............................................................. 433
Section 15 I
Figure 15.1 Block Diagram of I
Figure 15.2 I
Figure 15.3 I
Figure 15.4 I
Figure 15.5 I
Figure 15.6 Sample Flowchart for IIC Initialization .................................................................. 467
Figure 15.7 Sample Flowchart for Operations in Master Transmit Mode .................................. 468
Figure 15.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)........... 470
Figure 15.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 471
Figure 15.11 Master Receive Mode Operation Timing Example
Figure 15.12 Stop Condition Issuance Timing Example in Master Receive Mode
Figure 15.13 Sample Flowchart for Operations in Master Receive Mode
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
Figure 15.15 Master Receive Mode Operation Timing Example
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
Figure 15.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 479
Figure 15.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)....... 481
Figure 15.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)....... 481
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 482
Figure 15.21 Slave Receive Mode Operation Timing Example (1)
Figure 15.22 Slave Receive Mode Operation Timing Example (2)
Figure 15.23 Sample Flowchart for Slave Transmit Mode......................................................... 485
Figure 15.24 Slave Transmit Mode Operation Timing Example (MLS = 0).............................. 487
Figure 15.25 IRIC Setting Timing and SCL Control (1) ............................................................ 488
Figure 15.26 IRIC Setting Timing and SCL Control (2) ............................................................ 489
Figure 15.27 IRIC Setting Timing and SCL Control (3) ............................................................ 490
Figure 15.28 Block Diagram of Noise Canceler......................................................................... 492
Rev. 3.00, 03/04, page xxx of xl
(MLS = WAIT = 0) ................................................................................................. 470
2
2
2
2
2
(MLS = WAIT = 0, HNDS = 1)............................................................................. 473
(MLS = WAIT = 0, HNDS = 1)............................................................................. 473
(receiving multiple bytes) (WAIT = 1) .................................................................. 474
(receiving a single byte) (WAIT = 1) .................................................................... 475
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 477
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 478
(MLS = ACKB = 0, HNDS = 0)............................................................................ 484
(MLS = ACKB = 0, HNDS = 0)............................................................................ 484
C Bus Interface (IIC)
C Bus Interface Connections (Example: This LSI as Master) .............................. 437
C Bus Data Formats (I
C Bus Data Formats (Serial Formats)................................................................... 465
C Bus Timing........................................................................................................ 466
2
C Bus Interface ....................................................................... 436
2
C Bus Formats)................................................................ 465