DF2166VT33V Renesas Electronics America, DF2166VT33V Datasheet - Page 33

• Manufacturer Part Number: DF2166VT33V
• Description: IC H8S MCU FLASH 512K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Package: 144TQFP
• Family Name: H8S
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 106
• Number Of Timers: 5
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: DF2166VTE33V; DF2166VTE33V; HD64F2166VTE33V; HD64F2166VTE33V

Figure 15.29 Notes on Reading Master Receive Data ................................................................ 500
Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission
Figure 15.31 Stop Condition Issuance Timing ........................................................................... 502
Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 502
Figure 15.33 ICDR Register Read and ICCR Register Access Timing in Slave Transmit
Figure 15.34 TRS Bit Set Timing in Slave Mode....................................................................... 504
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost ...................................... 506
Section 16 LPC Interface (LPC)
Figure 16.1 Block Diagram of LPC............................................................................................ 508
Figure 16.2 Typical LFRAME Timing....................................................................................... 569
Figure 16.3 Abort Mechanism .................................................................................................... 569
Figure 16.4 SMIC Write Transfer Flow ..................................................................................... 570
Figure 16.5 SMIC Read Transfer Flow ...................................................................................... 571
Figure 16.6 BT Write Transfer Flow .......................................................................................... 572
Figure 16.7 BT Read Transfer Flow........................................................................................... 573
Figure 16.8 GA20 Output ........................................................................................................... 575
Figure 16.9 Power-Down State Termination Timing ................................................................. 580
Figure 16.10 SERIRQ Timing .................................................................................................... 581
Figure 16.11 Clock Start or Speed-Up........................................................................................ 583
Figure 16.12 HIRQ Flowchart (Example of Channel 1)............................................................. 586
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter ........................................................................... 589
Figure 17.2 D/A Converter Operation Example ......................................................................... 593
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 596
Figure 18.2 A/D Conversion Timing .......................................................................................... 602
Figure 18.3 External Trigger Input Timing ................................................................................ 603
Figure 18.4 A/D Conversion Accuracy Definitions.................................................................... 605
Figure 18.5 A/D Conversion Accuracy Definitions.................................................................... 605
Figure 18.6 Example of Analog Input Circuit ............................................................................ 606
Figure 18.7 Example of Analog Input Protection Circuit ........................................................... 608
Figure 18.8 Analog Input Pin Equivalent Circuit ....................................................................... 608
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Figure 20.1 Block Diagram of Flash Memory............................................................................ 612
Figure 20.2 Mode Transition of Flash Memory.......................................................................... 613
Figure 20.3 Flash Memory Configuration .................................................................................. 615
Figure 20.4 Block Division of User MAT .................................................................................. 617
Figure 20.5 Overview of User Procedure Program..................................................................... 618
Figure 20.6 System Configuration in Boot Mode....................................................................... 639
and Timing............................................................................................................. 501
Mode ...................................................................................................................... 503
Rev. 3.00, 03/04, page xxxi of xl