DF2166VT33V Renesas Electronics America, DF2166VT33V Datasheet - Page 570

• Manufacturer Part Number: DF2166VT33V
• Description: IC H8S MCU FLASH 512K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Package: 144TQFP
• Family Name: H8S
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 106
• Number Of Timers: 5
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: DF2166VTE33V; DF2166VTE33V; HD64F2166VTE33V; HD64F2166VTE33V

16.3.8
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor (this
LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are
allocated to the same address for both the host address and the slave address. TWR0MW is a
write-only register to the host processor, and a read-only register to the slave processor, while
TWR0SW is a write-only register to the slave processor and a read-only register to the host
processor. When the host and slave processors begin a write, after the respective TWR0 registers
have been written to, access right arbitration for simultaneous access is performed by checking the
status flags to see if those writes were valid. For the registers selected from the host according to
the I/O address, see section 16.3.4, LPC Channel 3 Address Register H, L (LADR3H, LADR3L).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host.
The initial values of TWR0 to TWR15 are undefined.
Rev. 3.00, 03/04, page 528 of 830