DF2166VT33V Renesas Electronics America, DF2166VT33V Datasheet - Page 405

• Manufacturer Part Number: DF2166VT33V
• Description: IC H8S MCU FLASH 512K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Package: 144TQFP
• Family Name: H8S
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 106
• Number Of Timers: 5
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: DF2166VTE33V; DF2166VTE33V; HD64F2166VTE33V; HD64F2166VTE33V

• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
[Legend]
*:
Bit
7
6
5
4
3
2
1
0
Don’t care.
Bit Name
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial Value
0
0
0
0
0
0
0
0
R/W Description
R/W Transmit Interrupt Enable
R/W Receive Interrupt Enable
R/W Transmit Enable
R/W Receive Enable
R/W Multiprocessor Interrupt Enable (enabled only when the
R/W Transmit End Interrupt Enable
R/W
R/W
When this bit is set to 1,a TXI interrupt request is
enabled.
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
When this bit is set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
Write 0 to this bit in smart card interface mode.
Clock Enable 1 and 0
These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 14.7.8, Clock Output Control.
When GM in SMR = 0
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1*: Reserved
When GM in SMR = 1
00: Output fixed to low
01: Clock output
10: Output fixed to high
11: Clock output
Rev. 3.00, 03/04, page 363 of 830