PIC16F684-E/P Microchip Technology, PIC16F684-E/P Datasheet - Page 79

• Manufacturer Part Number: PIC16F684-E/P
• Description: IC PIC MCU FLASH 2KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F684-E/P

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163029 - BOARD PICDEM FOR MECHATRONICSACICE0207 - MPLABICE 14P 300 MIL ADAPTER
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC5/CCP1/P1A pin
is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit, CCP1IF (PIR1<5>), is set.
FIGURE 11-2:
TABLE 11-2:
 2004 Microchip Technology Inc.
RC5/CCP1/P1A
0Bh/
8Bh
0Ch
0Eh
0Fh
10h
1Ah
13h
14h
15h
87h
8Ch
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture,
Addr
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• set the GO/DONE bit (ADCON0<1>)
pin
Output Enable
TRISC<5>
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON1
CCPR1L
CCPR1H
CCP1CON
TRISC
PIE1
Compare Mode
Name
Compare or Timer1 module.
Q
Special Event Trigger
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
CCP1CON<3:0>
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
R
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
S
P1M1
Mode Select
EEIF
EEIE
Bit 7
GIE
—
—
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set Flag bit CCP1IF
P1M0
(PIR1<5>)
ADIE
PEIE
ADIF
Bit 6
—
—
Match
CCPR1H CCPR1L
CCP1IE
CCP1IF
TRISC5
TMR1H
DC1B1
Bit 5
T0IE
Comparator
—
TMR1L
TRISC4
DC1B0
INTE
Bit 4
C2IF
C2IE
—
Preliminary
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
TRISC3
RAIE
C1IE
Bit 3
C1IF
—
11.2.1
The user must configure the RC5/CCP1/P1A pin as an
output by clearing the TRISC<5> bit.
11.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
11.2.3
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
The CCP1IF (PIR1<5>) bit is set, causing a ECCP
interrupt (if enabled). See Register 11-1.
11.2.4
In this mode (CCP1M<3:0> = 1011), an internal
hardware trigger is generated, which may be used to
initiate an action. See Register 11-1.
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1. The special event trigger output also starts an
A/D conversion (if the A/D module is enabled).
Note:
Note:
TRISC2
OSFIF
OSFIE
Bit 2
T0IF
—
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC5/CCP1/P1A compare output latch
to the default low level. This is not the
PORTC I/O data latch.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IF
TMR2IE
TRISC1
T1GSS
INTF
Bit 1
C2SYNC ---- --10 ---- --10
TMR1IF 0000 0000 0000 0000
TRISC0 --11 1111 --11 1111
TMR1IE 0000 0000 0000 0000
RAIF
Bit 0
PIC16F684
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOD
Value on
DS41202C-page 77
Value on
all other
Resets