AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 109
AT90PWM81-16SN
Manufacturer Part Number
AT90PWM81-16SN
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Height
2.35 mm
Length
13 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SN
Manufacturer:
Atmel
Quantity:
1 500
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12.5.3
12.6
12.6.1
7734P–AVR–08/10
Update of Values
Fifty Percent Waveform Configuration
Value Update Synchronization
When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a
Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and
OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not necessary to program
OCRnSAH/L and OCRnRAH/L registers.
The update of PSC waveform registers are done in the following way:
To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary,
all values can be updated at the same time at the end of the cycle by the PSC. The new set of values is cal-
culated by software and the update is initiated by software.
Figure 12-11. Update at the end of complete PSC cycle.
The software can stop the cycle before the end to update the values and restart a new PSC cycle.
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to LOCK
and AUTOLOCK configuration bits, the new whole set of values can be taken into account with the fol-
lowing conditions:
The registers which update is synchronized thanks to LOCK and AUTOLOCK are PSOCn, POM2,
OCRnSAH/L, OCRnRAH/L, OCRnSBH/L and OCRnRBH/L.
See these register’s description starting on
When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.
See “PSC 2 Configuration Register – PCNF2” on page 135.
Software
PSC
• Immediately when the PSC is stopped
• At the PSC end of cycle when the PSC is running
• At the PSC end of cycle following the required condition when LOCK or AUTOLOCK modes are
• When AUTOLOCK configuration is selected, the update of the PSC internal registers will be done at
• When LOCK configuration bit is set, there is no update. The update of the PSC internal registers will
used.
the end of the PSC cycle following a write in the Output Compare Register RB. The AUTOLOCK
configuration bit is taken into account at the end of the first PSC cycle.
be done at the end of the PSC cycle if the LOCK bit is released to zero.
Regulation Loop
Calculation
Cycle
With Set i
Cycle
With Set i
Cycle
With Set i
Writting in
PSC Registers
page
Cycle
With Set i
134.
End of Cycle
Request for
an Update
Cycle
With Set j
AT90PWM81
109
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