AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 135
AT90PWM81-16SN
Manufacturer Part Number
AT90PWM81-16SN
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Height
2.35 mm
Length
13 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SN
Manufacturer:
Atmel
Quantity:
1 500
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12.25.4
12.25.5
12.25.6
7734P–AVR–08/10
Output Compare SB Register – OCRnSBH and OCRnSBL
Output Compare RB Register – OCRnRBH and OCRnRBL
PSC 2 Configuration Register – PCNF2
Note : n = 0 to 2 according to PSC number.
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared
with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate
a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit tem-
porary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.
The PSC n Configuration Register is used to configure the running mode of the PSC.
• Bit 7 - PFIFTYn: PSC n Fifty
Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and OCRnSBH/L are
used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update of OCRnRBH/L. This fea-
ture is useful to perform fifty percent waveforms.
• Bit 6 - PALOCKn: PSC n Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSC
Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the PSC
internal registers will be done at the end of the PSC cycle if the Output Compare Register RB has been the
last written.
When set, this bit prevails over LOCK (bit 5)
• Bit 5 – PLOCKn: PSC n Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the
PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the
PSC internal registers will be done if the LOCK bit is released to zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
PFIFTY2
R/W
0
7
–
OCRnSB[7:0]
W
0
7
OCRnRB[15:12]
OCRnRB[7:0]
W
0
6
–
W
0
6
W
0
6
PALOCK2 PLOCK2
R/W
0
5
–
W
0
5
W
0
5
R/W
0
0
0
4
PMODE21 PMODE20 POP2
R/W
0
4
–
W
4
W
3
R/W
0
3
OCRnSB[11:8]
W
0
3
OCRnRB[11:8]
W
0
2
R/W
0
2
W
0
2
W
0
1
PCLKSEL2 POME2
R/W
0
1
W
0
1
W
0
AT90PWM81
0
R/W
0
0
W
0
0
W
0
PCNF2
OCRnSBH
OCRnSBL
OCRnRBH
OCRnRBL
135
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