AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 171

IC MCU AVR 8K FLASH ISP 20SOIC

AT90PWM81-16SN

Manufacturer Part Number
AT90PWM81-16SN
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet

Specifications of AT90PWM81-16SN

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Height
2.35 mm
Length
13 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM81-16SN
Manufacturer:
Atmel
Quantity:
1 500
13.22 Interrupts
13.22.1
13.23 PSCR Register Definition
13.23.1
7734P–AVR–08/10
List of Interrupt Vector
PSCR Synchro and Output Configuration – PSOC0
This section describes the specifics of the interrupt handling as performed in AT90PWM81.
The PSCR provides 3 interrupt vectors
See PSC0 Interrupt Mask Register
Bit
Read/Write
Initial Value
• Bit 7– PISEL0A1: PSC Input Select for part A
Together with PISEL0A0, defines active signal on PSCR part A.
Table 13-8.
• Bit 6– PISEL0B1: PSCR Input Select for part B
Together with PISEL0B0, defines active signal on PSCR part B.
Table 13-9.
PISEL0A1
0
0
1
1
PISEL0B1
0
0
1
1
• PSC0EC (End of Cycle): When enabled and when a match with OCRrRB occurs
• PSC0EEC (End of Enhanced Cycle): When enabled and when a match with OCRrRB occurs at the
• PSC0CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger,
15th enhanced cycle
capture of the PSCR counter or Synchro Error.
R/W
7
PISEL0A1
0
PSC trigger & fault input Selection
PSC trigger & fault input Selection
PISEL0A0
0
1
0
1
PISEL0B0
0
1
0
1
6
PISEL0B1 PSYNC01
R/W
0
5
R/W
0
page 177
Description
PSCIN0
Analog comparator output
PSCIN0A
PSCIN0B
Description
PSCIN0
Analog comparator output
PSCIN0A
PSCIN0B
and PSC0 Interrupt Flag Register
4
PSYNC00
R/W
0
3
-
R/W
0
2
POEN0B
R/W
0
1
R/W
0
-
page
AT90PWM81
178.
0
POEN0A
R/W
0
PSOC0
171

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