AT90PWM81-16SN Atmel, AT90PWM81-16SN Datasheet - Page 130

IC MCU AVR 8K FLASH ISP 20SOIC

AT90PWM81-16SN

Manufacturer Part Number
AT90PWM81-16SN
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet

Specifications of AT90PWM81-16SN

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Height
2.35 mm
Length
13 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM81-16SN
Manufacturer:
Atmel
Quantity:
1 500
12.20 Analog Synchronization
12.21 Interrupt Handling
130
AT90PWM81
PSC generates a signal to synchronize the sample and hold or the ADC start; synchronization is manda-
tory for measurements.
This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs as defined per
Table 12-11 on page 133
The signal can be shifted by a digital delay defined by the register PASDLY. The shifting clock can be
either Clkpsc or Clkpsc/4, as described per Bit 7, 6, 5– PASDLKn(2:0): Analog Synchronization Output
Delay or Input Blanking select .
Figure 12-40. Analog synchronization
As each PSC can be dedicated for one function, each PSC has its own interrupt system (vector ...)
List of interrupt sources:
• Counter reload (end of On Time 1)
• End of Enhanced Cycle
• PSC Input event (active edge or at the beginning of level configured event)
• PSC Mutual Synchronization Error
CLKPSCn/8
CLKPSCn/4
CLKPSCn/2
CLKPSCn
PASDLKn(2:0)
7
6
5
4
and
Table 12-12 on page
OCRnSA
match
OCRnRA
match
A Trig/Fault
Digital
Delay
PASDLYn
OCRnSB
match
134.
OCRnRB
match
B Trig/Fault
PASDLKn(2)
PSYNCn(1:0)
1
0
PSCnASY
7734P–AVR–08/10

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