PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 117

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.4
PORTC is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins and can tolerate input voltages
up to 5.5V.
PORTC is multiplexed with CCP, MSSP and EUSART
peripheral functions (Table 9-7). The pins have Schmitt
Trigger input buffers. The pins for CCP, SPI and
EUSART are also configurable for open-drain output
whenever these functions are active. Open-drain con-
figuration is selected by setting the SPIOD, CCPxOD,
and U1OD control bits (TRISG<7:5> and LATG<6>,
respectively).
RC1 is normally configured as the default peripheral
pin for the CCP2 module. Assignment of CCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
© 2007 Microchip Technology Inc.
Note:
PORTC, TRISC and
LATC Registers
These pins are configured as digital inputs
on any device Reset.
Preliminary
PIC18F85J90 FAMILY
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
RC<7:1> pins are multiplexed with LCD segment
drives, controlled by bits in the LCDSE1, LCDSE2,
LCDSE3 and LCDSE4 registers. I/O port functionality
is only available when the LCD segments are disabled.
EXAMPLE 9-3:
CLRF
CLRF
MOVLW
MOVWF
PORTC
LATC
0CFh
TRISC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
INITIALIZING PORTC
DS39770B-page 115