PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 291

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.2
For PIC18F85J90 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 22-1:
REGISTER 22-8:
TABLE 22-3:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
REGSLP
WDTPS3:WDTPS0
Name
R/W-0
All Device Resets
INTRC Oscillator
2:
Watchdog Timer (WDT)
(1)
The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
SWDTEN
CLRWDT
REGSLP
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator continues to operate normally in Sleep mode
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Sleep
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
U-0
—
WDT BLOCK DIAGRAM
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit 6
—
—
Enable WDT
W = Writable bit
‘1’ = Bit is set
U-0
—
WDT Counter
Bit 5
—
—
128
INTRC Control
4
U-0
Bit 4
—
Preliminary
Programmable Postscaler
RI
—
1:1 to 1:32,768
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
PIC18F85J90 FAMILY
TO
—
22.2.1
The WDTCON register (Register 22-8) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
U-0
—
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
Bit 2
PD
—
WDT
(2)
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
(1)
Reset
U-0
—
Bit 1
POR
—
x = Bit is unknown
SWDTEN
U-0
Bit 0
BOR
—
DS39770B-page 289
Wake-up from
Power-Managed
Modes
WDT
Reset
Reset Values
SWDTEN
on page
R/W-0
52
52
bit 0
(2)