PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 405

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
RESET ............................................................................. 325
Reset .................................................................................. 45
Resets .............................................................................. 283
RETFIE ............................................................................ 326
RETLW ............................................................................. 326
RETURN .......................................................................... 327
Return Address Stack ........................................................ 59
Return Stack Pointer (STKPTR) ........................................ 60
RLCF ................................................................................ 327
RLNCF ............................................................................. 328
RRCF ............................................................................... 328
RRNCF ............................................................................. 329
S
SCK .................................................................................. 185
SDI ................................................................................... 185
SDO ................................................................................. 185
SEC_IDLE Mode ................................................................ 42
SEC_RUN Mode ................................................................ 38
Serial Clock, SCK ............................................................. 185
Serial Data In (SDI) .......................................................... 185
Serial Data Out (SDO) ..................................................... 185
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 329
Slave Select (SS) ............................................................. 185
SLEEP .............................................................................. 330
Sleep
Software Simulator (MPLAB SIM) .................................... 346
DS39770B-page 404
OSCTUNE (Oscillator Tuning) ................................... 31
PIE1 (Peripheral Interrupt Enable 1) ........................ 101
PIE2 (Peripheral Interrupt Enable 2) ........................ 102
PIE3 (Peripheral Interrupt Enable 3) ........................ 103
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 98
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 99
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 100
RCON (Reset Control) ....................................... 46, 107
RCSTA1 (EUSART Receive Status and Control) .... 231
RCSTA2 (AUSART Receive Status and Control) .... 251
SSPCON1 (MSSP Control 1, I
SSPCON1 (MSSP Control 1, SPI Mode) ................. 187
SSPCON2 (MSSP Control 2, I
SSPCON2 (MSSP Control 2, I
SSPSTAT (MSSP Status, I
SSPSTAT (MSSP Status, SPI Mode) ...................... 186
STATUS ..................................................................... 73
STKPTR (Stack Pointer) ............................................ 60
T0CON (Timer0 Control) .......................................... 131
T1CON (Timer1 Control) .......................................... 135
T2CON (Timer2 Control) .......................................... 141
T3CON (Timer3 Control) .......................................... 143
TXSTA1 (EUSART Transmit Status and Control) .... 230
TXSTA2 (AUSART Transmit Status and Control) .... 250
WDTCON (Watchdog Timer Control) ....................... 289
Brown-out Reset (BOR) ............................................. 45
MCLR Reset, During Power-Managed Modes ........... 45
MCLR Reset, Normal Operation ................................ 45
Power-on Reset (POR) .............................................. 45
RESET Instruction ..................................................... 45
Stack Full Reset ......................................................... 45
Stack Underflow Reset .............................................. 45
Watchdog Timer (WDT) Reset ................................... 45
Brown-out Reset (BOR) ........................................... 283
Oscillator Start-up Timer (OST) ............................... 283
Power-on Reset (POR) ............................................ 283
Power-up Timer (PWRT) ......................................... 283
OSC1 and OSC2 Pin States ...................................... 36
2
C Mode) ....................... 195
2
2
2
C Mode) ................. 196
C Master Mode) ..... 197
C Slave Mode) ....... 198
Preliminary
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 283
SPI Mode (MSSP)
SS .................................................................................... 185
SSPOV ............................................................................ 219
SSPOV Status Flag ......................................................... 219
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 61
SUBFSR .......................................................................... 341
SUBFWB ......................................................................... 330
SUBLW ............................................................................ 331
SUBULNK ........................................................................ 341
SUBWF ............................................................................ 331
SUBWFB ......................................................................... 332
SWAPF ............................................................................ 332
T
Table Pointer Operations (table) ........................................ 84
Table Reads/Table Writes ................................................. 61
TBLRD ............................................................................. 333
TBLWT ............................................................................. 334
Timer0 .............................................................................. 131
Timer1 .............................................................................. 135
Associated Registers ............................................... 193
Bus Mode Compatibility ........................................... 193
Effects of a Reset .................................................... 193
Enabling SPI I/O ...................................................... 189
Master Mode ............................................................ 190
Master/Slave Connection ......................................... 189
Operation ................................................................. 188
Operation in Power-Managed Modes ...................... 193
Serial Clock .............................................................. 185
Serial Data In ........................................................... 185
Serial Data Out ........................................................ 185
Slave Mode .............................................................. 191
Slave Select ............................................................. 185
Slave Select Synchronization .................................. 191
SPI Clock ................................................................. 190
Typical Connection .................................................. 189
R/W Bit ............................................................ 199, 201
Associated Registers ............................................... 133
Clock Source Select (T0CS Bit) ............................... 132
Operation ................................................................. 132
Overflow Interrupt .................................................... 133
Prescaler ................................................................. 133
Prescaler Assignment (PSA Bit) .............................. 133
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 133
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 132
Source Edge Select (T0SE Bit) ............................... 132
16-Bit Read/Write Mode .......................................... 137
Associated Registers ............................................... 139
Interrupt ................................................................... 138
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Oscillator, as Secondary Clock .................................. 31
Overflow Interrupt .................................................... 135
Resetting, Using the CCP Special Event Trigger .... 138
TMR1H Register ...................................................... 135
TMR1L Register ....................................................... 135
Use as a Clock Source ............................................ 137
Use as a Real-Time Clock ....................................... 138
Switching Assignment ..................................... 133
Layout Considerations ..................................... 138
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