PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 398

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

INDEX
A
A/D ................................................................................... 263
Absolute Maximum Ratings ............................................. 349
AC (Timing) Characteristics ............................................. 366
ACKSTAT ........................................................................ 219
ACKSTAT Status Flag ..................................................... 219
ADCAL Bit ........................................................................ 271
ADCON0 Register ............................................................ 263
ADCON1 Register ............................................................ 263
ADCON2 Register ............................................................ 263
ADDFSR .......................................................................... 338
ADDLW ............................................................................ 301
Addressable Universal Synchronous Asynchronous Receiver
ADDULNK ........................................................................ 338
ADDWF ............................................................................ 301
ADDWFC ......................................................................... 302
ADRESH Register ............................................................ 263
ADRESL Register .................................................... 263, 266
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 302
ANDWF ............................................................................ 303
Assembler
© 2007 Microchip Technology Inc.
A/D Converter Interrupt, Configuring ....................... 267
Acquisition Requirements ........................................ 268
ADCAL Bit ................................................................ 271
ADCON0 Register .................................................... 263
ADCON1 Register .................................................... 263
ADCON2 Register .................................................... 263
ADRESH Register ............................................ 263, 266
ADRESL Register .................................................... 263
Analog Port Pins, Configuring .................................. 269
Associated Registers ............................................... 271
Automatic Acquisition Time ...................................... 269
Calibration ................................................................ 271
Configuring the Module ............................................ 267
Conversion Clock (T
Conversion Requirements ....................................... 385
Conversion Status (GO/DONE Bit) .......................... 266
Conversions ............................................................. 270
Converter Characteristics ........................................ 384
Operation in Power-Managed Modes ...................... 271
Special Event Trigger (CCP) .................................... 270
Use of the CCP2 Trigger .......................................... 270
Load Conditions for Device Timing Specifications ... 367
Parameter Symbology ............................................. 366
Temperature and Voltage Specifications ................. 367
Timing Conditions .................................................... 367
GO/DONE Bit ........................................................... 266
Transmitter (AUSART). See AUSART.
MPASM Assembler .................................................. 346
AD
) ........................................... 269
Preliminary
PIC18F85J90 FAMILY
AUSART
Auto-Wake-up on Sync Break Character ......................... 242
B
Baud Rate Generator ...................................................... 215
BC .................................................................................... 303
BCF ................................................................................. 304
BF .................................................................................... 219
BF Status Flag ................................................................. 219
Bias Generation (LCD)
Block Diagrams
Asynchronous Mode ................................................ 254
Baud Rate Generator (BRG) ................................... 252
Synchronous Master Mode ...................................... 258
Synchronous Slave Mode ........................................ 261
Charge Pump Design Considerations ..................... 167
A/D ........................................................................... 266
Analog Input Model .................................................. 267
AUSART Receive .................................................... 256
AUSART Transmit ................................................... 254
Baud Rate Generator .............................................. 215
Capture Mode Operation ......................................... 150
Comparator Analog Input Model .............................. 277
Comparator I/O Operating Modes ........................... 274
Comparator Output .................................................. 276
Comparator Voltage Reference ............................... 280
Comparator Voltage Reference Output Buffer Example
Compare Mode Operation ....................................... 151
Connections for On-Chip Voltage Regulator ........... 290
Device Clock .............................................................. 29
EUSART Receive .................................................... 240
EUSART Transmit ................................................... 238
External Power-on Reset Circuit (Slow V
Fail-Safe Clock Monitor ........................................... 292
Generic I/O Port Operation ...................................... 109
Interrupt Logic ............................................................ 94
LCD Clock Generation ............................................. 162
LCD Driver Module .................................................. 157
LCD Regulator Connections (M0 and M1) .............. 164
MSSP (I
MSSP (I
MSSP (SPI Mode) ................................................... 185
On-Chip Reset Circuit ................................................ 45
PIC18F6XJ90 ............................................................ 10
PIC18F8XJ90 ............................................................ 11
Associated Registers, Receive ........................ 257
Associated Registers, Transmit ....................... 255
Receiver .......................................................... 256
Setting up 9-Bit Mode with Address Detect ..... 256
Transmitter ...................................................... 254
Associated Registers ....................................... 252
Baud Rate Error, Calculating ........................... 252
Baud Rates, Asynchronous Modes ................. 253
High Baud Rate Select (BRGH Bit) ................. 252
Operation in Power-Managed Modes .............. 252
Sampling ......................................................... 252
Associated Registers, Receive ........................ 260
Associated Registers, Transmit ....................... 259
Reception ........................................................ 260
Transmission ................................................... 258
Associated Registers, Receive ........................ 262
Associated Registers, Transmit ....................... 261
Reception ........................................................ 262
Transmission ................................................... 261
281
47
2
2
C Master Mode) ........................................ 213
C Mode) .................................................... 194
DS39770B-page 397
DD
Power-up)