PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 166

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
15.3.3
PIC18F85J90 family devices have four distinct circuit
configurations for LCD bias generation:
• M0: Regulator with Boost
• M1: Regulator without Boost
• M2: Resistor Ladder with Software Contrast
• M3: Resistor Ladder with Hardware Contrast
15.3.3.1
In M0 operation, the LCD charge pump feature is
enabled. This allows the regulator to generate voltages
up to +3.6V to the LCD (as measured at LCDBIAS3).
M0 uses a flyback capacitor connected between
V
LCDBIAS0 through LCDBIAS3, to obtain the required
voltage boost (Figure 15-3). The output voltage (V
is the difference of potential between LCDBIAS3 and
LCDBIAS0. It is set by the BIAS2:BIAS0 bits which
adjust the offset between LCDBIAS0 and V
back capacitor (C
ment for large LCD loads. This mode is useful in those
cases where the voltage requirements of the LCD are
higher than the microcontroller’s V
software control of the display’s contrast by adjustment
of bias voltage by changing the value of the BIAS bits.
M0 supports Static and 1/3 Bias types. Generation of
the voltage levels for 1/3 Bias is handled automatically,
but must be configured in software.
FIGURE 15-3:
DS39770B-page 164
LCAP
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
1 and V
BIAS CONFIGURATIONS
M0 (Regulator with Boost)
based on the actual LCD specifications.
LCAP
FLY
2, as well as filter capacitors on
) acts as a charge storage ele-
LCD REGULATOR CONNECTIONS FOR M0 AND M1 CONFIGURATIONS
PIC18F85J90
LCDBIAS3
LCDBIAS2
LCDBIAS1
LCDBIAS0
V
V
LCAP
LCAP
DD
AV
. It also permits
DD
1
2
(V
SS
V
BIAS
. The fly-
DD
Mode 0
BIAS
up to 3.6V)
Preliminary
)
C
0.047 F
C3
0.047 F
C2
0.047 F
C1
0.047 F
C0
0.047 F
FLY
(1)
(1)
(1)
(1)
(1)
M0 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
setting the CPEN bit. If static Bias type is required, the
MODE13 bit must be cleared.
15.3.3.2
M1 operation is similar to M0, but does not use the LCD
charge pump. It can provide V
level supplied directly to LCDBIAS3. It can be used in
cases where V
never drop below a level that can provide adequate
contrast for the LCD. The connection of external com-
ponents is very similar to M0, except that LCDBIAS3
must be tied directly to V
The BIAS<2:0> bits can still be used to adjust contrast
in software by changing V
these bits changes the offset between LCDBIAS0 and
V
LCDBIAS0 and the voltage tied to LCDBIAS3. Thus, if
V
M0, the level of V
Like
types.Generation of the voltage levels for 1/3 Bias is
handled automatically but must be configured in
software.
M1 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
clearing the CPEN bit. If 1/3 Bias type is required, the
MODE13 bit should also be set.
SS
DD
. In M1, this is reflected in the change between the
should change, V
M0,
M1
M1 (Regulator without Boost)
DD
BIAS
(V
supports
for the application is expected to
BIAS
Mode 1
is constant.
BIAS
V
V
© 2007 Microchip Technology Inc.
DD
DD
DD
BIAS
V
C
0.047 F
C2
0.047 F
C1
0.047 F
C0
0.047 F
will also change; where in
(Figure 15-3).
DD
FLY
Static
. As with M0, changing
)
BIAS
(1)
(1)
(1)
(1)
up to the voltage
and
1/3
Bias