PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 36

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
2.4.2
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3:
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-4. In
this configuration, the divide-by-4 output on OSC2 is
not available.
FIGURE 2-4:
DS39770B-page 34
Clock from
Ext. System
Clock from
Ext. System
EXTERNAL CLOCK INPUT
(EC MODES)
F
or RA6
Open
OSC
/4
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1/CLKI
OSC2/CLKO
OSC1
OSC2
PIC18F85J90
PIC18F85J90
(HS Mode)
Preliminary
2.4.3
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The
FOSC2:FOSC0 Configuration bits (CONFIG2L<2:0>)
to either ‘110’ (for ECPLL) or ‘100’ (for HSPLL). In
addition, the PLLEN bit (OSCTUNE<6>) must also be
set. Clearing PLLEN disables the PLL, regardless of
the chosen oscillator configuration. It also allows
additional flexibility for controlling the application’s
clock speed in software.
FIGURE 2-5:
HSPLL or ECPLL (CONFIG2L)
OSC2
OSC1
PLL
PLL Enable (OSCTUNE)
HS or EC
PLL FREQUENCY MULTIPLIER
Mode
is
enabled
F
F
IN
OUT
PLL BLOCK DIAGRAM
4
© 2007 Microchip Technology Inc.
Comparator
by
Loop
Filter
Phase
VCO
programming
SYSCLK
the