PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 73

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 5-3:
© 2007 Microchip Technology Inc.
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LCDPS
LCDSE0
LCDCON
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
Legend:
Note 1:
Filename
(2)
(2)
2:
3:
4:
5:
(2)
(2)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise it is disabled and reads as ‘0’. See Section 2.4.3 “PLL
Frequency Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
EUSART Baud Rate Generator
EUSART Receive Register
EUSART Transmit Register
EEPROM Control Register 2 (not a physical register)
TRISA7
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
TRISH7
TRISE7
TRISD7
TRISC7
TRISB7
LCDEN
TRISJ7
TRISF7
SPIOD
LATH7
LATE7
LATD7
LATC7
LATB7
CSRC
LATJ7
LATF7
SPEN
U2OD
SE07
Bit 7
WFT
—
—
—
—
—
—
—
PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
(5)
(5)
TRISA6
CCP2OD
PLLEN
BIASMD
LATA6
TRISH6
TRISE6
TRISD6
TRISC6
TRISB6
TRISJ6
TRISF6
SLPEN
LATH6
LATE6
LATD6
LATC6
LATB6
LCDIP
LCDIF
LCDIE
LATJ6
LATF6
U1OD
SE06
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
RX9
TX9
—
(5)
(4)
(5)
CCP1OD
TRISH5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
TRISJ5
TRISF5
WERR
RC2IP
RC2IE
RC1IP
RC1IE
LATH5
LATE5
LATD5
LATC5
LATB5
SREN
RC2IF
RC1IF
LATJ5
LATF5
LATA5
TXEN
LCDA
TUN5
SE05
Bit 5
—
—
—
—
—
TRISG4
TRISH4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
TRISJ4
TRISF4
LATG4
LATH4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
SYNC
CREN
TX2IP
TX2IE
TX1IP
TX1IE
LATJ4
FREE
TX2IF
TX1IF
TUN4
SE04
Bit 4
WA
—
—
—
—
Preliminary
WRERR
TRISG3
SENDB
ADDEN
TRISH3
TRISF3
TRISE3
TRISD3
TRISC3
TRISB3
TRISA3
TRISJ3
LATG3
SSPIP
SSPIE
LATH3
LATF3
LATE3
LATD3
LATC3
LATB3
BCLIP
BCLIF
BCLIE
SSPIF
LATJ3
LATA3
TUN3
SE03
Bit 3
CS1
LP3
—
—
—
PIC18F85J90 FAMILY
CCP2IP
CCP2IE
TRISG2
CCP2IF
TRISH2
TRISF2
TRISD2
TRISC2
TRISB2
TRISA2
TRISJ2
WREN
LATG2
BRGH
LATH2
LATF2
LATD2
LATC2
LATB2
LATA2
FERR
LVDIP
LVDIF
LVDIE
LATJ2
TUN2
SE02
Bit 2
CS0
LP2
—
—
—
—
—
2
C™ Slave mode. See Section 16.4.3.2 “Address
CCP1IP
CCP1IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISG1
CCP1IF
TRISH1
TRISF1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LMUX1
TRISJ1
LATH1
LATG1
LATD1
LATC1
OERR
LATF1
LATE1
LATB1
LATA1
TRMT
LATJ1
TUN1
SE01
Bit 1
LP1
WR
TMR1IP
TMR1IF
TMR1IE
TRISH0
TRISG0
TRISD0
TRISC0
TRISE0
TRISB0
TRISA0
LMUX0
TRISJ0
LATH0
LATG0
LATD0
LATC0
LATE0
LATB0
LATA0
LATJ0
TX9D
RX9D
TUN0
SE00
Bit 0
LP0
—
—
—
—
—
—
—
—
—
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
000- 0000
---- ----
---0 x00-
-111 -11-
-000 -00-
-000 -00-
11-- 111-
00-- 000-
00-- 000-
-111 1-11
-000 0-00
-000 0-00
0000 0000
1111 1111
1111 1111
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
00-x xxxx
xxxx xxx-
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
POR, BOR
DS39770B-page 71
Value on
on page
Details
53, 233
53, 241
53, 239
53, 230
53, 231
53, 159
53, 160
53, 158
54, 106
54, 100
54, 103
54, 105
54, 102
54, 104
54, 101
54, 130
54, 128
54, 126
54, 124
54, 121
54, 119
54, 117
54, 114
54, 130
54, 128
54, 126
54, 124
54, 121
54, 119
54, 117
54, 114
54, 111
54, 111
53, 82
53, 83
54, 99
54, 98
31, 54