PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 259

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

FIGURE 18-5:
TABLE 18-5:
© 2007 Microchip Technology Inc.
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2
TXSTA2
SPBRG2
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
RX2 (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third
Name
word causing the OERR (Overrun) bit to be set.
AUSART Receive Register
AUSART Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
LCDIE
LCDIP
LCDIF
Bit 6
RX9
TX9
bit 1
RC2IE
RC2IP
RC2IF
SREN
TXEN
Bit 5
bit 7/8
Preliminary
Stop
INT0IE
bit
TX2IF
TX2IE
TX2IP
CREN
SYNC
Bit 4
Word 1
RCREG2
Start
bit
PIC18F85J90 FAMILY
bit 0
ADDEN
RBIE
Bit 3
—
—
—
—
TMR0IF
CCP2IE
CCP2IP
bit 7/8 Stop
CCP2IF
Word 2
RCREG2
BRGH
FERR
Bit 2
bit
CCP1IF
CCP1IE
CCP1IP
INT0IF
OERR
Start
TRMT
bit
Bit 1
bit 7/8
RX9D
TX9D
RBIF
DS39770B-page 257
Bit 0
—
—
—
Stop
bit
on Page
Values
Reset
51
54
54
54
56
56
56
56