PIC18F27J13-I/SS Microchip Technology, PIC18F27J13-I/SS Datasheet

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PIC18F27J13-I/SS

Manufacturer Part Number
PIC18F27J13-I/SS
Description
IC PIC MCU 128KB FLASH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SS

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
SSOP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
19
Number Of Timers
8
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18F47J13 Family
Data Sheet
28/44-Pin, High-Performance
Microcontrollers with
nanoWatt XLP Technology
Preliminary
 2010 Microchip Technology Inc.
DS39974A

Related parts for PIC18F27J13-I/SS

PIC18F27J13-I/SS Summary of contents

Page 1

... Microchip Technology Inc. PIC18F47J13 Family Data Sheet 28/44-Pin, High-Performance Microcontrollers with nanoWatt XLP Technology Preliminary DS39974A ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart - Pulse steering control  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Peripheral Highlights (cont.): • Seven Capture/Compare/PWM (CCP) modules • Two Master Synchronous Serial Port (MSSP) modules featuring: ...

Page 4

... PIC18F47J13 FAMILY PIC18F Device PIC18F26J13 28 64K 3760 19 PIC18F27J13 28 128K 3760 19 PIC18F46J13 44 64K 3760 25 PIC18F47J13 44 128K 3760 25 PIC18LF26J13 28 64K 3760 19 PIC18LF27J13 28 128K 3760 19 PIC18LF46J13 44 64K 3760 25 PIC18LF47J13 44 128K 3760 25 DS39974A-page 4 MSSP 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 4/4 3 Preliminary  2010 Microchip Technology Inc. ...

Page 5

... Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 1 ...

Page 6

... Section 10.7 “Peripheral Pin Select (PPS)”. For the QFN package recommended that the bottom pad be connected to V Note: DS39974A-page 6 OSC2/CLKO/RA6 33 1 OSC1/CLKI/RA7 PIC18F4XJ13 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD 25 9 RA5/AN4/C1INC/SS1/HLVDIN/RP2 DDCORE 11 Preliminary = Pins are up to 5.5V tolerant CAP . SS  2010 Microchip Technology Inc. ...

Page 7

... Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”. For the QFN package recommended that the bottom pad be connected to V Note:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 28 1 ...

Page 8

... Packaging Information.............................................................................................................................................................. 529 Appendix A: Revision History............................................................................................................................................................. 541 Appendix B: Migration From PIC18F46J11 to PIC18F47J13............................................................................................................. 541 The Microchip Web Site ..................................................................................................................................................................... 555 Customer Change Notification Service .............................................................................................................................................. 555 Customer Support .............................................................................................................................................................................. 555 Reader Response .............................................................................................................................................................................. 556 Product Identification System............................................................................................................................................................. 557 DS39974A-page 8 Preliminary  2010 Microchip Technology Inc. ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Preliminary DS39974A-page 9 ...

Page 10

... PIC18F47J13 FAMILY NOTES: DS39974A-page 10 Preliminary  2010 Microchip Technology Inc. ...

Page 11

... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F26J13 • PIC18LF26J13 • PIC18F27J13 • PIC18LF27J13 • PIC18F46J13 • PIC18LF46J13 • PIC18F47J13 • PIC18LF47J13 1.1 Core Features 1.1.1 nanoWatt XLP TECHNOLOGY All of the devices in the PIC18F47J13 family incorpo- rate a range of features that can significantly reduce power consumption during operation ...

Page 12

... V pin while 2.0V-3.6V can be supplied to DDCORE V (V should never exceed V DD DDCORE For more details about the internal voltage regulator, see Section 27.3 “On-Chip Voltage Regulator”. Preliminary  2010 Microchip Technology Inc. but should DD, through ...

Page 13

... ECCP and 7 CCP MSSP (2), Enhanced USART (2) Yes 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 44-Pin QFN and TQFP Preliminary PIC18F27J13 DC – 48 MHz 128 65,536 3.8 PIC18F47J13 DC – 48 MHz 128 65,536 3 ...

Page 14

... Timer6 EUSART1 Preliminary PORTA Data Latch RA0:RA7 (1) Data Memory (3.8 Kbytes) Address Latch 12 PORTB (1) RB0:RB7 12 4 Access FSR0 Bank FSR1 FSR2 12 PORTC (1) RC0:RC7 inc/dec logic Address Decode 8 PRODH PRODL Multiply ALU<8> 8 Timer8 Comparators MSSP1 MSSP2 EUSART2  2010 Microchip Technology Inc. ...

Page 15

... Timer0 Timer1 CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 Note 1: See Table 1-3 for I/O port pin descriptions. 2: The on-chip voltage regulator is always enabled by default.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Data Latch 8 8 Data Memory (3 ...

Page 16

... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL/DIG Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 17

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. 27 I/O TTL/DIG Digital I/O ...

Page 18

... I/O TTL/DIG Digital I/O. I Analog Analog Input 9. I Analog Comparator 3 Input CTMU edge 2 Input. I ST/DIG Remappable Peripheral Pin 6 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 19

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) (2) 22 ...

Page 20

... Capture/Compare/PWM input/output Asynchronous serial receive data input. I/O ST/DIG Synchronous serial data output/input. I/O ST/DIG Remappable Peripheral Pin 18 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 21

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer Type Type 28-QFN 5 P — ...

Page 22

... RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL/DIG Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 23

... DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer 44- Type Type TQFP PORTA is a bidirectional I/O port ...

Page 24

... Analog Input 9. I Analog Comparator 3 Input CTMU Edge 2 input. O DIG Parallel Master Port address. I/O ST/DIG Remappable Peripheral Pin 6 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 25

... DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer 44- Type Type TQFP ...

Page 26

... ST/DIG Remappable Peripheral Pin 15 input/output I/O ST/DIG Digital I/O. O DIG SPI data output. I/O ST/DIG Remappable Peripheral Pin 16 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 27

... DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer 44- Type Type TQFP ...

Page 28

... Remappable Peripheral Pin 23 input/output. (3) (3) 5 I/O ST/DIG Digital I/O. I/O ST/TTL/ Parallel Master Port data. DIG I/O ST/DIG Remappable Peripheral Pin 24 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Preliminary Description ) specific  2010 Microchip Technology Inc. ...

Page 29

... DIG = Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: 5.5V tolerant. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Buffer 44- Type Type TQFP PORTE is a bidirectional I/O port ...

Page 30

... PIC18F47J13 FAMILY NOTES: DS39974A-page 30 Preliminary  2010 Microchip Technology Inc. ...

Page 31

... Note: AV pins must always be connected, SS regardless of whether any of the analog modules are being used. On other pack- age types, the AV and AV DD internally connected to the V The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 2- MCLR (2) ...

Page 32

... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXJXX JP C1 and V specifications are met and V specifications are met. IL  2010 Microchip Technology Inc. ...

Page 33

... Frequency (MHz) Data for Murata GRM21BF50J106ZE01 shown. Note: Measurements at 25° bias.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ...

Page 34

... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS Preliminary SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1  2010 Microchip Technology Inc. ...

Page 35

... RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output stops when in Sleep mode, but will continue during Idle mode (see Figure 3-1).  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 3-1: OSCILLATOR MODES ...

Page 36

... MHz 100 500 kHz 011 250 kHz 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> Preliminary 48 MHz  2 Primary Clock IDLE Source CPU 00 Peripherals (3) 01 RA6 11  4 OSCCON<1:0> CLKO Enabled Modes WDT, PWRT, FSCM and Two-Speed Start-up  2010 Microchip Technology Inc. ...

Page 37

... DD See the notes following Table 3-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 3-3: Osc Type HS the crystal Capacitor values are for design guidance only. ...

Page 38

... Two-Speed Start-up These features are discussed in larger detail in Section 27.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 42). Preliminary  2010 Microchip Technology Inc. ...

Page 39

... The low-frequency INTRC oscillator operates indepen- dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...

Page 40

... When the CFGPLLEN Configuration bit is used to enable the PLL, clearing OSCTUNE<6> will not disable Note 1: the PLL. DS39974A-page 40 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 41

... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor (FSCM).  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.3.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’ ...

Page 42

... Clock transitions are discussed in more detail in Section 4.1.2 “Entering Power-Managed Modes”. (1) R/W-0 R-1 U-1 IRCF0 OSTS — Unimplemented bit ‘0’ = Bit is cleared (3) (1) Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 43

... Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. Note 1: Default output frequency of INTOSC on Reset (4 MHz). 2: When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no 3: effect.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY (2) R/W-1 R/W-0 R/W-1 (3) SOSCDRV SOSCGO — ...

Page 44

... R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) is used as the base clock; the base clock reflects any clock switching of the device Preliminary R/W-0 R/W-0 R/W-0 RODIV1 RODIV0 bit Bit is unknown (1)  2010 Microchip Technology Inc. ...

Page 45

... PMP, INTx pins, etc.). Peripherals that may add significant current consumption Section 30.2 “DC Characteristics: Power-Down and Supply Current PIC18F47J13 Family (Industrial)”.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.6 Power-up Delays Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applica- tions ...

Page 46

... PIC18F47J13 FAMILY NOTES: DS39974A-page 46 Preliminary  2010 Microchip Technology Inc. ...

Page 47

... Selecting a power-managed mode requires these decisions: • Will the CPU be clocked? • If so, which clock source will be used?  2010 Microchip Technology Inc. PIC18F47J13 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking and the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1 ...

Page 48

... If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN and DSEN at that time. If IDLEN or DSEN have changed, the device will enter the new SOSCRUN power-managed mode specified by the new setting. Preliminary  2010 Microchip Technology Inc. ...

Page 49

... Counter SCS<1:0> Bits Changed Note 1024 OST OSC  2010 Microchip Technology Inc. PIC18F47J13 FAMILY The Timer1 oscillator should already be Note: running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the ...

Page 50

... SCS bits are not affected by the switch. The INTRC clock source will continue to run if either the WDT or the FSCM is enabled. block (see n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition OSTS Bit Set = 2 ms (approx). These intervals are not shown to scale. PLL Preliminary  2010 Microchip Technology Inc. ...

Page 51

... OST OSC PLL  2010 Microchip Technology Inc. PIC18F47J13 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 27 ...

Page 52

... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. Preliminary  2010 Microchip Technology Inc CSD ...

Page 53

... TRANSITION TIMING FOR ENTRY TO IDLE MODE OSC1 CPU Clock Peripheral Clock Program PC Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event  2010 Microchip Technology Inc. PIC18F47J13 FAMILY CSD PC Preliminary DS39974A-page 53 ...

Page 54

... The loss of a currently selected clock source (if the FSCM is enabled) 4.5.3 EXIT BY RESET Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. Preliminary  2010 Microchip Technology Inc. , following the wake CSD (see Section 4.2 “Run ...

Page 55

... Executing one single-cycle NOP instruction • Executing the SLEEP instruction immediately after setting DSEN and the single NOP (no interrupts in between)  2010 Microchip Technology Inc. PIC18F47J13 FAMILY In order to minimize the possibility of inadvertently enter- ing Deep Sleep, the DSEN bit is cleared in hardware two instruction cycles after having been set ...

Page 56

... Sleep. The reference clock source is configured through the DSWDTOSC bit. DSWDT is enabled through the DSWDTEN bit. Entering Deep Sleep mode automatically clears the DSWDT. See Section 27.0 “Special Features of the CPU” for more information. Preliminary Wake-up Event Considerations  2010 Microchip Technology Inc. ...

Page 57

... Determine if the device exited Deep Sleep by reading the Deep Sleep bit, DS (WDTCON<3>). This bit will be set if there was an exit from Deep Sleep mode.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 14. Clear the Deep Sleep bit, DS (WDTCON<3>). 15. Determine the wake-up source by reading the DSWAKEH and DSWAKEL registers ...

Page 58

... DSBOR arming voltage during Deep Sleep, DD DSBOR did not drop below the DSBOR arming voltage during Deep DD is initially applied. Preliminary R/W-0 R/W-0 R/W-0 r DSULPEN RTCWDIS bit Bit is unknown (1) (1) R/W-0 R/W-0 R/W-0 DSBOR RELEASE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 59

... Unimplemented: Read as ‘0’ bit 0 DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep  2010 Microchip Technology Inc. PIC18F47J13 FAMILY (1) R/W-xxxx U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared drops below the normal BOR threshold outside of Deep ...

Page 60

... Unlike the other bits in this register, this bit can be set outside of Deep Sleep. Note 1: DS39974A-page 60 R/W-0 R/W-0 R/W-0 DSWDT DSRTC DSMCLR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — DSPOR bit Bit is unknown (1)  2010 Microchip Technology Inc. ...

Page 61

... ULPSINK bits in the WDTCON register. 7. Configure Sleep mode. 8. Enter Sleep mode.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY When the voltage on RA0 drops below V will be generated, which will cause the device to wake-up and execute the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode ...

Page 62

... Deep Sleep OSCCONbits.IDLEN = 0; // enable deep sleep DSCONHbits.DSEN = 1; // Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) DS39974A-page 62 Preliminary  2010 Microchip Technology Inc. ...

Page 63

... RTCCMD PMDIS0 ECCP3MD ECCP2MD ECCP1MD Not implemented on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: To prevent accidental RTCC changes, the RTCCMD bit is normally locked. Use the following unlock sequence (with 2: interrupts disabled) to successfully modify the RTCCMD bit: 1. Write 55h to EECON2. ...

Page 64

... PIC18F47J13 FAMILY NOTES: DS39974A-page 64 Preliminary  2010 Microchip Technology Inc. ...

Page 65

... BOR circuit is only implemented on “F” devices always used, except while in Deep DDCORE Sleep mode. The V DDCORE  2010 Microchip Technology Inc. PIC18F47J13 FAMILY For information on WDT Resets, see Section 27.2 “Watchdog Timer (WDT)”. For Stack Reset events, see Section 6.1.4.4 “Stack Full and Underflow Resets” ...

Page 66

... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39974A-page 66 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 67

... DDCORE the Deep Sleep BOR circuit is enabled by the SS DSBOREN bit (CONFIG3L<2> = 1), it will monitor V  2010 Microchip Technology Inc. PIC18F47J13 FAMILY If V drops below the V DD will be held in a Reset state similar to POR. All registers will be set back to their POR Reset values and the con- tents of the DSGPR0 and DSGPR1 holding registers will be lost ...

Page 68

... PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure 5-4). This is useful for testing purposes or to synchronize more than one PIC18F device operating in parallel. T PWRT Preliminary ) for PWRT , V RISE < PWRT  2010 Microchip Technology Inc. ...

Page 69

... FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET  2010 Microchip Technology Inc. PIC18F47J13 FAMILY T PWRT T PWRT , V RISE > 3. PWRT Preliminary ...

Page 70

... Reset. Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by POR and BOR, MCLR and WDT Resets and WDT wake-ups. RCON Register ( POR Preliminary STKPTR Register BOR STKFUL STKUNF  2010 Microchip Technology Inc. ...

Page 71

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep ...

Page 72

... Preliminary  2010 Microchip Technology Inc. Wake-up via WDT or Interrupt N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu ...

Page 73

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep ...

Page 74

... Preliminary  2010 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu (3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uxuu uuuu uxuu ...

Page 75

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep ...

Page 76

... Preliminary  2010 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- uuuu uu-- uuuu uuuu uuuu ...

Page 77

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep ...

Page 78

... Preliminary  2010 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ...

Page 79

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: Not implemented on PIC18F2XJ13 devices. 5: Not implemented on “LF” devices. 6:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep ...

Page 80

... PIC18F47J13 FAMILY NOTES: DS39974A-page 80 Preliminary  2010 Microchip Technology Inc. ...

Page 81

... Config. Words Unimplemented Read as ‘0’ Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. Note:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space ...

Page 82

... Additional details on the device Configuration Words are provided in Section 27.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION WORD FOR PIC18F47J13 FAMILY DEVICES Program Device Memory (Kbytes) PIC18F26J13 64 PIC18F46J13 PIC18F27J13 128 PIC18F47J13 Preliminary  2010 Microchip Technology Inc. Configuration Word Addresses FFF8h to FFFFh 1FFF8h to 1FFFFh ...

Page 83

... TOSH TOSL 00h 1Ah 34h  2010 Microchip Technology Inc. PIC18F47J13 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...

Page 84

... Stack Pointer. The previous value st push pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 SP1 SP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 85

... SUB1 · · RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...

Page 86

... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1  2010 Microchip Technology Inc. ...

Page 87

... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF  2010 Microchip Technology Inc. PIC18F47J13 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...

Page 88

... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary  2010 Microchip Technology Inc. ...

Page 89

... Bank 15 60h FFh Note 1: Addresses, EB0h through F5Fh, are not part of the Access Bank. Either the BANKED or the MOVFF instruction should be used to access these SFRs.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 000h Access RAM 05Fh 060h GPR 0FFh ...

Page 90

... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upward toward the bottom of the SFR area. GPRs are not initialized by a POR and are unchanged on all other Resets. Preliminary (2) From Opcode  2010 Microchip Technology Inc. ...

Page 91

... PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. Reserved; do not write to this location. 5:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. ...

Page 92

... ED0h RPOR16 EB0h — ECFh RPOR15 ECEh RPOR14 ECDh RPOR13 ECCh RPOR12 ECBh RPOR11 ECAh RPOR10 EC9h RPOR9 EC8h RPOR8 EC7h RPOR7 EC6h RPOR6 EC5h RPOR5 EC4h RPOR4 EC3h RPOR3 EC2h RPOR2 EC1h RPOR1 EC0h RPOR0  2010 Microchip Technology Inc. ...

Page 93

... Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR ...

Page 94

... FAFh RCREG1 EUSART1 Receive Register FAEh TXREG1 EUSART1 Transmit Register FADh TXSTA1 CSRC TX9 Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: DS39974A-page 94 Bit 5 Bit 4 Bit 3 Bit 2 — ...

Page 95

... F7Fh SPBRGH1 EUSART1 Baud Rate Generator High Byte F7Eh BAUDCON1 ABDOVF RCIDL Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY ...

Page 96

... Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) F4Dh DSCONH DSEN — F4Ch DSCONL — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: DS39974A-page 96 Bit 5 Bit 4 ...

Page 97

... Capture/Compare/PWM Register 7 Low Byte F09h CCP7CON — — F08h CCPR8H Capture/Compare/PWM Register 8 High Byte Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY ...

Page 98

... ED8h RPOR24 — — (2) ED7h RPOR23 — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3: DS39974A-page 98 Bit 5 Bit 4 Bit 3 Bit 2 DC8B1 DC8B0 CCP8M3 ...

Page 99

... EB1h — — — EB0h — — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Note 1: Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 2: Value on POR, BOR. 3:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Bit 5 Bit 4 ...

Page 100

... The C and DC bits operate as Borrow and Note: Digit subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) th low-order bit of the result occurred th low-order bit of the result Preliminary Borrow bits, respectively in R/W-x R/W-x (1) ( bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 101

... LSB. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 “General Purpose  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Register File” location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit, ‘ ...

Page 102

... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF INDF1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory  2010 Microchip Technology Inc. ...

Page 103

... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...

Page 104

... Figure 6-9. Those who desire to use byte or bit-oriented instruc- tions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 28.2.1 “Extended Instruction Syntax”. Preliminary  2010 Microchip Technology Inc. ...

Page 105

... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 000h 060h Bank 0 100h Bank 1 through ...

Page 106

... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank  2010 Microchip Technology Inc. ...

Page 107

... TBLPTRL Program Memory (TBLPTR) The Table Pointer register points to a byte in program memory. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 108

... Reset or a write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Preliminary Table Latch (8-bit) TABLAT  2010 Microchip Technology Inc. ...

Page 109

... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-x R/W-0 FREE ...

Page 110

... Figure 7-3 illustrates the relevant boundaries of the TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> Preliminary TBLPTRL 0  2010 Microchip Technology Inc. ...

Page 111

... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD  2010 Microchip Technology Inc. PIC18F47J13 FAMILY The TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. ...

Page 112

... The CPU will stall for the duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary  2010 Microchip Technology Inc. ...

Page 113

... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...

Page 114

... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block Preliminary  2010 Microchip Technology Inc. ...

Page 115

... EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN  2010 Microchip Technology Inc. PIC18F47J13 FAMILY on the second table write.) 3. Set the WREN bit (EECON1<2>) to enable writes and the WPROG bit (EECON1<5>) to select Word Write mode. 4. Disable interrupts. ...

Page 116

... See Section 27.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 5 Bit 4 Bit 3 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TMR0IE INT0IE RBIE WPROG FREE WRERR Preliminary Bit 2 Bit 1 Bit 0 TMR0IF INT0IF RBIF WREN WR —  2010 Microchip Technology Inc. ...

Page 117

... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply  2010 Microchip Technology Inc. PIC18F47J13 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...

Page 118

... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H  2010 Microchip Technology Inc. ...

Page 119

... Individual interrupts can be disabled through their corresponding enable bits.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...

Page 120

... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary  2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...

Page 121

... None of the RB<7:4> pins have changed state A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T Note 1: condition and allow the bit to be cleared.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Interrupt flag bits are set when an interrupt Note: ...

Page 122

... This feature allows for software polling. DS39974A-page 122 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 123

... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 ...

Page 124

... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 125

... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY U-0 R/W-0 R/W-0 — BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...

Page 126

... RTCCIF: RTCC Interrupt Flag bit RTCC interrupt occurred (must be cleared in software RTCC interrupt occurred DS39974A-page 126 R-0 R/W-0 R/W-0 TX2IF TMR4IF CTMUIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR3GIF RTCCIF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 127

... A TMR register capture occurred (must be cleared in software TMR register capture occurred Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Unused in this mode.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘ ...

Page 128

... TMR gate interrupt occurred (must be cleared in software TMR gate interrupt occurred DS39974A-page 128 R/W-0 R/W-0 R/W-0 TMR8IF TMR6IF TMR5IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR5GIF TMR1GIF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 129

... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt These bits are unimplemented on 28-pin devices. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...

Page 130

... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39974A-page 130 U-0 R/W-0 R/W-0 — BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...

Page 131

... Enabled 0 = Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 132

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TMR8IE TMR6IE TMR5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP4IE CCP3IE bit Bit is unknown R/W-0 R/W-0 TMR5GIE TMR1GIE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 133

... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority These bits are unimplemented on 28-pin devices. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ...

Page 134

... Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS39974A-page 134 U-0 R/W-1 R/W-1 — BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-1 R/W-1 TMR3IP CCP2IP bit Bit is unknown ...

Page 135

... Low priority bit 1 TMR3GIP: Timer3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CTMUIP U = Unimplemented bit, read as ‘0’ ...

Page 136

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TMR8IP TMR6IP TMR5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown R/W-1 R/W-1 TMR5GIP TMR1GIP bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 137

... For details on bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 5-1.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...

Page 138

... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine (ISR). ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary  2010 Microchip Technology Inc. ...

Page 139

... EN RD PORT Note 1: I/O pins have diode protection  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...

Page 140

... TTL buffers with the PMPTTL bit in the PADCFG1 reg- ister (Register 10-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. By default, these PMP inputs use the port’s ST buffers. Preliminary  2010 Microchip Technology Inc. + ...

Page 141

... ECCP2OD: ECCP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 ECCP1OD: ECCP1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U = Unimplemented bit, read as ‘0’ ...

Page 142

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 U2OD U1OD bit Bit is unknown R/W-0 R/W-0 SPI2OD SPI1OD ...

Page 143

... CMxCON registers. To use RAx as digital inputs necessary to turn off the comparators Power-on Reset (POR), RA5 and Note: RA<3:0> are configured as analog inputs and read as ‘0’.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY U-0 U-0 R/W-0 (1) — ...

Page 144

... PORTA<3> data input; disabled when analog input is enabled. I ANA A/D Input Channel 3 and Comparator C1+ input. Default input configuration on POR. I ANA Comparator 1 Input B I ANA A/D and comparator voltage reference high input. Preliminary Description output is enabled. REF  2010 Microchip Technology Inc. ...

Page 145

... HLVDCON VDIRMAG BGVST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. These bits are only available in 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and Note 1: PIC18LF47J13).  2010 Microchip Technology Inc. PIC18F47J13 FAMILY I/O I/O Type O DIG LATA<5> data output; not affected by analog input. ...

Page 146

... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/CCP5/PMA0/KBI1/RP8 pin. Preliminary  2010 Microchip Technology Inc. ...

Page 147

... ANCON1 register. All other pin functions are disabled when ICSP™ or ICD is enabled. 2: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). 4:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY I/O ...

Page 148

... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting Note 1: the appropriate bits in the ANCON1 register. All other pin functions are disabled when ICSP™ or ICD is enabled. 2: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). 4: DS39974A-page 148 I/O I/O Type O DIG LATB< ...

Page 149

... ANCON1 register. All other pin functions are disabled when ICSP™ or ICD is enabled. 2: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). 4: TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name ...

Page 150

... BSF ANCON1,PCFG11 Preliminary INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<5:0> as inputs ; RC<7:6> as outputs ; ANCON register is not in Access Bank ;Configure RC2/AN11 as digital input  2010 Microchip Technology Inc. ...

Page 151

... C/SMB = I C/SMBus input buffer Don’t care (TRISx bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and Note 1: PIC18LF47J13).  2010 Microchip Technology Inc. PIC18F47J13 FAMILY I/O I/O Type I ST PORTC< ...

Page 152

... LATC3 TRISC5 TRISC4 TRISC3 — PCFG12 PCFG11 CPOL EVPOL1 EVPOL0 RTCWREN RTCSYNC HALFSEC Preliminary Description Bit 2 Bit 1 Bit 0 RC2 RC1 RC0 LATC2 LATC1 LATC0 TRISC2 TRISC1 TRISC0 PCFG10 PCFG9 PCFG8 CREF CCH1 CCH0 RTCOE RTCPTR1 RTCPTR0  2010 Microchip Technology Inc. ...

Page 153

... PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output POR, these pins are configured as Note: digital inputs.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY EXAMPLE 10-5: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ...

Page 154

... Remappable Peripheral Pin 21 output PORTD<5> data input. O DIG LATD<5> data output. I ST/TTL Parallel Master Port data in. O DIG Parallel Master Port data out Remappable Peripheral Pin 22 input. O DIG Remappable Peripheral Pin 22 output. Preliminary Description 2 2 C/SMB = I C/SMBus  2010 Microchip Technology Inc. ...

Page 155

... LATD LATD7 LATD6 (1) TRISD TRISD7 TRISD6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. These registers are not available in 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and Note 1: PIC18LF26J13).  2010 Microchip Technology Inc. PIC18F47J13 FAMILY I/O I/O Type ...

Page 156

... V levels. DD Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB. Preliminary  2010 Microchip Technology Inc. ...

Page 157

... ANCON0 PCFG7 PCFG6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. These registers and/or bits are not available in 28-pin devices (PIC18F26J13, PIC18F27J13, Note 1: PIC18LF26J13 and PIC18LF26J13). bit 7 RDPU: PORTD Pull-up Enable bit Note All PORTD pull-ups are disabled ...

Page 158

... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or an output is being mapped. Preliminary  2010 Microchip Technology Inc change notifica- ...

Page 159

... SPI2 Slave Select Input PWM Fault Input Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY with one of the pin selectable peripherals. Programming a given peripheral’s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral ...

Page 160

... ECCP2 Compare or PWM Output ECCP2 Enhanced PWM Output, Channel B ECCP2 Enhanced PWM Output, Channel C ECCP2 Enhanced PWM Output, Channel D ECCP3 Compare or PWM Output ECCP3 Enhanced PWM Output, Channel B ECCP3 Enhanced PWM Output, Channel C ECCP3 Enhanced PWM Output, Channel D Preliminary  2010 Microchip Technology Inc. ...

Page 161

... If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.7.4.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be con- figured to prevent more than one write session to the RPINRx and RPORx registers ...

Page 162

... EECON2 Write Protect PPS BSF PPSCON, IOLOCK, BANKED If the Configuration bit, IOL1WAY = 1, Note: once the IOLOCK bit is set, it cannot be cleared, preventing any future RP register changes. The IOLOCK bit is cleared back to ‘0’ on any device Reset. Preliminary  2010 Microchip Technology Inc. ...

Page 163

... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Input and output register values can only be Note: changed if IOLOCK (PPSCON<0> See Example 10-7 for a specific command sequence ...

Page 164

... R/W-1 R/W-1 T3CKR4 T3CKR3 T3CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INTR3R1 INTR3R0 bit Bit is unknown R/W-1 R/W-1 T0CKR1 T0CKR0 bit Bit is unknown R/W-1 R/W-1 T3CKR1 T3CKR0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 165

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R<4:0>: Assign Input Capture 3 (ECCP3) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 IC1R4 IC1R3 IC1R2 U = Unimplemented bit, read as ‘ ...

Page 166

... R/W-1 R/W-1 T5GR4 T5GR3 T5GR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 T1GR1 T1GR0 bit Bit is unknown R/W-1 R/W-1 T3GR1 T3GR0 bit Bit is unknown R/W-1 R/W-1 T5GR1 T5GR0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 167

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 CK2R<4:0>: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-1 R/W-1 R/W-1 RX2DT2R4 RX2DT2R3 RX2DT2R2 U = Unimplemented bit, read as ‘0’ ...

Page 168

... R/W-1 R/W-1 SS2R4 SS2R3 SS2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 SDI2R1 SDI2R0 bit Bit is unknown R/W-1 R/W-1 SCK2R1 SCK2R0 bit Bit is unknown R/W-1 R/W-1 SS2R1 SS2R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 169

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 OCFAR4 OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘ ...

Page 170

... R/W-0 R/W-0 RP2R4 RP2R3 RP2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP1R1 RP1R0 bit Bit is unknown R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 171

... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-14 for peripheral function numbers)  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP3R4 RP3R3 RP3R2 U = Unimplemented bit, read as ‘ ...

Page 172

... R/W-0 R/W-0 RP8R4 RP8R3 RP8R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP6R1 RP6R0 bit Bit is unknown R/W-0 R/W-0 RP7R1 RP7R0 bit Bit is unknown R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 173

... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-14 for peripheral function numbers)  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 RP9R3 RP9R2 U = Unimplemented bit, read as ‘ ...

Page 174

... R/W-0 R/W-0 RP14R4 RP14R3 RP14R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP12R1 RP12R0 bit Bit is unknown R/W-0 R/W-0 RP13R1 RP13R0 bit Bit is unknown R/W-0 R/W-0 RP14R1 RP14R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 175

... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 10-14 for peripheral function numbers)  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP15R4 RP15R3 RP15R2 U = Unimplemented bit, read as ‘ ...

Page 176

... R/W-0 R/W-0 RP20R4 RP20R3 RP20R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown (1) R/W-0 R/W-0 RP19R1 RP19R0 bit Bit is unknown (1) R/W-0 R/W-0 RP20R1 RP20R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 177

... Unimplemented: Read as ‘0’ bit 4-0 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 10-14 for peripheral function numbers) RP23 pins are not available on 28-pin devices. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 ...

Page 178

... Table 10-14 for peripheral function numbers) RP24 pins are not available on 28-pin devices. Note 1: DS39974A-page 178 R/W-0 R/W-0 R/W-0 RP24R4 RP24R3 RP24R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 RP24R1 RP24R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 179

... PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13. FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Key features of the PMP module are: • bits of Addressing when using Data/Address Multiplexing • Programmable Address Lines • One Chip Select Line • ...

Page 180

... R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (Register 11-1 and registers (Register 11-3 and (Register 11-5 and (1) R/W-0 R/W-0 PTWREN PTRDEN bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 181

... For Master Mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) This register is only available on 44-pin devices. Note 1: These bits have no effect when their corresponding pins are used as address lines. 2:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY (2) (2) U-0 R/W-0 — ...

Page 182

... Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) This register is only available on 44-pin devices. Note 1: DS39974A-page 182 R/W-0 R/W-0 R/W-0 INCM1 INCM0 MODE16 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 MODE1 MODE0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 183

... Wait Wait This register is only available on 44-pin devices. Note 1: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. 2:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase ...

Page 184

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PTEN4 PTEN3 PTEN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 PTEN9 PTEN8 bit Bit is unknown (1) R/W-0 R/W-0 PTEN1 PTEN0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 185

... OB<3:0>E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted This register is only available on 44-pin devices. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY U-0 R-0 R-0 — ...

Page 186

... This option allows users to select either the normal Schmitt Trigger input buffer on digital I/O pins shared with the PMP, or use TTL level compatible buffers instead. Buffer configuration is controlled by the PMPTTL bit in the PADCFG1 register. Preliminary  2010 Microchip Technology Inc. ...

Page 187

... Value at POR ‘1’ = Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. Note 1:  2010 Microchip Technology Inc. PIC18F47J13 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> ...

Page 188

... Figure 11-2 displays the connection of the PSP. When chip select is active and a write strobe occurs and (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the PMDIN1L register. PIC18 Slave PMD<7:0> PMCS PMRD PMWR Preliminary Address Bus Data Bus Control Lines  2010 Microchip Technology Inc. ...

Page 189

... PMCS PMWR PMRD PMD<7:0> IBF OBE PMPIF  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented on to PMD<7:0>. Figure 11-4 provides the timing for the control signals in Read mode ...

Page 190

... Buffer registers should be read to clear the IBxF flags. If these flags are not cleared, then there is a risk of hitting an overflow condition. PIC18 Slave Write PMD<7:0> Address Address Pointer Pointer PMDOUT1L (0) PMCS PMDOUT1H (1) PMDOUT2L (2) PMRD PMDOUT2H (3) PMWR Preliminary  2010 Microchip Technology Inc. Read PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) ...

Page 191

... ADDR<1:0>. Table 11-1 provides the corresponding FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 11-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 ...

Page 192

... When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are written. If any buffer is already written (IBxF = 1), the next write strobe to that buffer will generate an OBUF event and the byte will be discarded Preliminary  2010 Microchip Technology Inc ...

Page 193

... Configuration is controlled by separate bits in the PMCONL register. Note that the polarity of control signals that share the  2010 Microchip Technology Inc. PIC18F47J13 FAMILY same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used ...

Page 194

... PMRD Data Bus PMWR Control Lines PMD<7:0> PMA<7:0> PMCS PMALL Address Bus Multiplexed PMRD Data and Address Bus PMWR Control Lines PMD<7:0> PMA<13:8> PMCS PMALL PMALH Multiplexed Data and PMRD Address Bus PMWR Control Lines Preliminary  2010 Microchip Technology Inc. ...

Page 195

... Then, the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register.  2010 Microchip Technology Inc. PIC18F47J13 FAMILY If the 16-bit mode is enabled (MODE16 = 1), the read of the low byte of the PMDIN1L register will initiate two bus reads ...

Page 196

... FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS Address<7:0> PMD<7:0> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> DS39974A-page 196 Data Data WAITE<1:0> WAITM<3:0> = 0010 Preliminary  2010 Microchip Technology Inc. ...

Page 197

... Address<7:0> PMD<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 Data Preliminary ...

Page 198

... PMCS Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY DS39974A-page 198 Data Address<13:8> Data Address<13:8> Data Preliminary  2010 Microchip Technology Inc. ...

Page 199

... Q1 PMCS PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY  2010 Microchip Technology Inc. PIC18F47J13 FAMILY LSB MSB LSB MSB LSB MSB Preliminary ...

Page 200

... PMALH PMALL PMPIF BUSY FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY DS39974A-page 200 LSB MSB Address<13:8> LSB Address<13:8> LSB Preliminary MSB MSB  2010 Microchip Technology Inc. ...

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