PIC18F27J13-I/SS Microchip Technology, PIC18F27J13-I/SS Datasheet - Page 230

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PIC18F27J13-I/SS

Manufacturer Part Number
PIC18F27J13-I/SS
Description
IC PIC MCU 128KB FLASH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SS

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
SSOP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
19
Number Of Timers
8
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18F47J13 FAMILY
15.6
The TMRx register pair (TMRxH:TMRxL) increments
from 0000h to FFFFh and overflows to 0000h. The
Timerx interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMRxIF.
Table 15-3 gives each module’s flag bit.
TABLE 15-3:
This interrupt can be enabled or disabled by setting or
clearing the TMRxIE bit, respectively. Table 15-4 gives
each module’s enable bit.
TABLE 15-4:
DS39974A-page 230
Timer Module
Timer Module
3
5
3
5
Timer3/5 Interrupt
TIMER3/5 INTERRUPT FLAG
BITS
TIMER3/5 INTERRUPT
ENABLE BITS
PIR2<1>
PIR5<1>
PIE2<1>
PIE5<2>
Flag Bit
Flag Bit
Preliminary
15.7
If the ECCP modules are configured to use Timerx and
to generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timerx.
The trigger from ECCP2 will also start an A/D conver-
sion if the A/D module is enabled. (For more informa-
tion, see Section 19.3.4 “Special Event Trigger”.)
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for TimerX.
If Timerx is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timerx coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
Note:
Note:
Resetting Timer3/5 Using the
ECCP Special Event Trigger
The Special Event Triggers from the
ECCPx module will only clear the TMR3
register’s content, but not set the TMR3IF
interrupt flag bit (PIR1<0>).
The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see Register 18-3 and
Register 19-2.
 2010 Microchip Technology Inc.

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