PIC18F27J13-I/SS Microchip Technology, PIC18F27J13-I/SS Datasheet - Page 313

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PIC18F27J13-I/SS

Manufacturer Part Number
PIC18F27J13-I/SS
Description
IC PIC MCU 128KB FLASH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SS

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
SSOP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
19
Number Of Timers
8
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
REGISTER 20-7:
 2010 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN
R/W-0
bit 7
2:
3:
(3)
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I
(or writes to the SSPxBUF are disabled).
This bit is not implemented in I
GCEN: General Call Enable bit (Slave mode only)
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address is disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit;
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive is Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition is Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition is Idle
SEN: Start Condition Enable bit
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition is Idle
ACKSTAT
2
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
automatically cleared by hardware
R-0
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
(1, ACCESS FC5h; 2, F71h)
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(1)
2
C Master mode.
ACKEN
(2)
(2)
2
C
R/W-0
Preliminary
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
PIC18F47J13 FAMILY
RCEN
R/W-0
(3)
(2)
(2)
(1)
2
PEN
R/W-0
C™ MASTER MODE)
(2)
x = Bit is unknown
RSEN
R/W-0
(2)
DS39974A-page 313
SEN
R/W-0
bit 0
(2)

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