ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 249
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Using the
Boundary-scan
Chain
Using the On-chip
Debug System
2467V–AVR–02/11
•
•
•
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note:
For detailed information on the JTAG specification, refer to the literature listed in
on page
A complete description of the Boundary-scan capabilities are given in the section
(JTAG) Boundary-scan” on page
As shown in
•
•
•
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped location which is part of the communication interface between the CPU and the
JTAG system.
The Break point Unit implements Break on Change of Program Flow, Single Step Break, two
Program Memory Breakpoints, and two combined break points. Together, the four break points
can be configured as either:
•
•
•
•
•
on the TDO pin. The JTAG Instruction selects a particular Data Register as path between
TDI and TDO and controls the circuitry surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is
latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-
IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register – Shift-DR state. While in this state, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI
input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must
be held low during input of all bits except the MSB. The MSB of the data is shifted in when
this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin,
the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the
TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
A scan chain on the interface between the internal AVR CPU and the internal peripheral
units
Break point unit
Communication interface between the CPU and JTAG system
4 single Program Memory break points
3 Single Program Memory break point + 1 single Data Memory break point
2 single Program Memory break points + 2 single Data Memory break points
2 single Program Memory break points + 1 Program Memory break point with mask (“range
break point”)
2 single Program Memory break points + 1 Data Memory break point with mask “range
break point”.
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for 5 TCK clock periods.
251.
Figure
120, the hardware support for On-chip Debugging consists mainly of
252.
ATmega128
“Bibliography”
“IEEE 1149.1
249
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