ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 288
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 288 of 385
- Download datasheet (8Mb)
Latching of Fuses
288
ATmega128
Table 118. Fuse High Byte
Notes:
Table 119. Fuse Low Byte
Notes:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
The Fuse values are latched when the device enters Programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
Fuse High
Byte
OCDEN
JTAGEN
SPIEN
CKOPT
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low
Byte
BODLEVEL
BODEN
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN fuse is not accessible in SPI Serial Programming mode.
2. The CKOPT fuse functionality depends on the setting of the CKSEL bits. See
3. The default value of BOOTSZ1..0 results in maximum Boot Size. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of lock bits
5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This
1. The default value of SUT1..0 results in maximum start-up time. See
2. The default setting of CKSEL3..0 results in Internal RC Oscillator @ 1MHz. See
(2)
(4)
(5)
Sources” on page 36
and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system
to be running in all sleep modes. This may increase the power consumption.
to avoid static current at the TDO pin in the JTAG interface.
details.
page 36
Bit No.
Bit No.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
for details.
Description
Enable OCD
Enable JTAG
Enable
Data Downloading
Oscillator options
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
for details)
Select Boot Size (see
for details)
Select Reset Vector
Description
Brown out detector trigger level
Brown out detector enable
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
Serial Program and
for details.
Table 112
Table 112
Default Value
1 (unprogrammed)
1 (unprogrammed, BOD disabled)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
Default Value
1 (unprogrammed, OCD
disabled)
0 (programmed, JTAG enabled)
0 (programmed, SPI prog.
enabled)
1 (unprogrammed)
1 (unprogrammed, EEPROM not
preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
(1)
(2)
(2)
(2)
(3)
(3)
(1)
(2)
Table 14 on page 41
Table 112 on page 284
2467V–AVR–02/11
Table 6 on
“Clock
for
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