ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 255
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (8Mb)
SAMPLE_PRELOAD;
$2
AVR_RESET; $C
BYPASS; $F
Boundary-scan
Related Register in
I/O Memory
MCU Control and
Status Register –
MCUCSR
Boundary-scan
Chain
2467V–AVR–02/11
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latched are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the Reset will be active as long as there
is a logic 'one' in the Reset Chain. The output from this chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
The MCU Control and Status Register contains control bits for general MCU functions, and pro-
vides information on which reset source caused an MCU Reset.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit
is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the
JTAG interface, a timed sequence must be followed when changing this bit: The application soft-
ware must write this bit to the desired value twice within four cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
Bit
Read/Write
Initial Value
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However,
the output latches are not connected to the pins.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
R/W
JTD
7
0
R
6
–
0
R
5
–
0
JTRF
R/W
4
WDRF
R/W
3
See Bit Description
BORF
R/W
2
EXTRF
R/W
1
PORF
ATmega128
R/W
0
MCUCSR
255
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