AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 237

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.13 Slave Mode
19.13.1
19.13.2
Figure 19-23. Slave Mode Typical Application Block Diagram
19.13.3
19.13.4
19.13.4.1
32059K–03/2011
Definition
Application Block Diagram
Programming Slave Mode
Receiving Data
Read Sequence
Host with
Interface
Master
TWI
The Slave Mode is defined as a mode where the device receives the clock and the address from
another device called the master.
In this mode, the device never initiates and never completes the transmission (START,
REPEATED_START and STOP conditions are always provided by the master).
The following fields must be programmed before entering Slave mode:
As the device receives the clock, values written in CWGR are not taken into account.
After a Start or Repeated Start condition is detected and if the address sent by the Master
matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave
ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a
condition is detected, EOSACC (End Of Slave ACCess) flag is set.
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the THR (TWI
Transmit Holding Register) until a STOP condition or a REPEATED_START + an address differ-
ent from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission
Complete) flag is set and SVACC reset.
As soon as data is written in the THR, TXRDY (Transmit Holding Register Ready) flag is reset,
and it is set when the shift register is empty and the sent data acknowledged or not. If the data is
not acknowledged, the NACK flag is set.
TWD
TWCK
1. SADR (SMR): The slave device address is used in order to be accessed by master
2. MSDIS (CR): Disable the master mode.
3. SVEN (CR): Enable the slave mode.
devices in read or write mode.
Host with TWI
Interface
Slave 1
Host with TWI
Interface
Slave 2
LCD Controller
Slave 3
R
R
AT32UC3B
VDD
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