AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 262

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 20-3. SSC Functional Block Diagram
20.7.1
32059K–03/2011
Peripheral
CLK_SSC
Clock Management
Bus
DMA
Interface
Divider
Clock
User
Interrupt Controller
The transmitter clock can be generated by:
The receiver clock can be generated by:
Furthermore, the transmitter block can generate an external clock on the TX_CLOCK pin, and
the receiver block can generate an external clock on the RX_CLOCK pin.
This allows the SSC to support many Master and Slave Mode data transfers.
Interrupt Control
• an external clock received on the TX_CLOCK pin
• the receiver clock
• the internal clock divider
• an external clock received on the RX_CLOCK pin
• the transmitter clock
• the internal clock divider
TX_FRAME_SYNC
RX_FRAME_SYNC
TX_FRAME_SYNC
RX_FRAME_SYNC
TX_CLOCK Input
RX_CLOCK
TX clock
RX clock
Input
Selector
Selector
Start
TX_DMA
Start
RX_DMA
Load Shift
Load Shift
Transmitter
Transmit Clock
Receive Clock
Controller
Controller
Receiver
Transmit Holding
Receive Holding
Register
Register
Transmit Shift Register
Receive Shift Register
RX clock
TX clock
Holding Register
Holding Register
Transmit Sync
Receive Sync
Clock Output
Clock Output
Frame Sync
Frame Sync
Controller
Controller
Controller
Controller
AT32UC3B
RX_CLOCK
RX_FRAME_SYNC
TX_CLOCK
TX_FRAME_SYNC
RX_DATA
TX_DATA
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