AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 452

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.8.3
22.8.3.1
Register Name:
Access Type:
Offset:
Reset Value:
• RESUME: Send USB Resume
• RESET: Send USB Reset
• SOFE: Start of Frame Generation Enable
32059K–03/2011
31
23
15
7
-
-
-
-
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset
is being sent.
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).
USB Host Registers
Host General Control Register
30
22
14
6
-
-
-
-
UHCON
Read/Write
0x0400
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
RESUME
26
18
10
2
-
-
-
RESET
25
17
9
1
-
-
-
AT32UC3B
SOFE
24
16
8
0
-
-
-
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