AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 528

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32059K–03/2011
• the waveform period. This channel parameter is defined in the CPRD field of the CPRDx
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the CDTYx
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (CLK_PWM) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (CLK_PWM) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the CMRx register. By default the signal starts by
a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the CMRx register. The default mode is left aligned.
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
CLK_PWM
X CPRD
CRPD
2
2
CLK_PWM
duty cycle
CLK_PWM
×
×
×
duty cycle
CLK_PWM
X CPRD
CPRD DIVA
×
×
DIVA
)
×
=
)
)
=
or
(
------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
(
---------------------------------------------------------------------------------------------------------------------- -
)
(
period 2 ⁄
(
--------------------------------------------- -
or
CRPD
CLK_PWM
(
--------------------------------------------------- -
2 CPRD
–
×
×
CLK_PWM
DIVAB
⁄
) 1 fchannel_x_clock
–
×
period
⁄
(
)
DIVB
period 2 ⁄
)
)
×
CDTY
×
CDTY
)
) )
AT32UC3B
528