AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 447

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.8.2.18
Register Name:
Access Type:
Offset:
Reset Value:
• HSBADDR: HSB Address
32059K–03/2011
31
23
15
7
This field determines the HSB bus current address of a channel transfer.
The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,
HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access
byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the
end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.
Device DMA Channel n HSB Address Register
30
22
14
6
UDDMAnADDR, n in [1..6]
Read/Write
0x0314 + (n - 1) * 0x10
0x00000000
29
21
13
5
28
20
12
HSBADDR[31:24]
HSBADDR[23:16]
4
HSBADDR[15:8]
HSBADDR[7:0]
27
19
11
3
26
18
10
2
25
17
9
1
AT32UC3B
24
16
8
0
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