AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 562

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.7.6
Name:
Access Type:
Offset:
Reset Value:
• RXBUFF: RX Buffer Full
• ENDRX: End of RX Buffer
• GOVRE: General Overrun Error
• DRDY: Data Ready
• OVREn: Overrun Error n
• EOCn: End of Conversion n
32059K–03/2011
OVRE7
EOC7
31
23
15
–
–
7
This bit is set when the Buffer Full signal from the Peripheral DMA is active.
This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive.
This bit is set when the End Receive signal from the Peripheral DMA is active.
This bit is cleared when the End Receive signal from the Peripheral DMA is inactive.
This bit is set when a General Overrun Error has occurred.
This bit is cleared when the SR register is read.
1: At least one General Overrun Error has occurred since the last read of the SR register.
0: No General Overrun Error occurred since the last read of the SR register.
This bit is set when a data has been converted and is available in the LCDR register.
This bit is cleared when the LCDR register is read.
0: No data has been converted since the last read of the LCDR register.
1: At least one data has been converted and is available in the LCDR register.
These bits are set when an overrun error on the corresponding channel has occurred (if implemented).
These bits are cleared when the SR register is read.
0: No overrun error on the corresponding channel (if implemented) since the last read of SR.
1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR.
These bits are set when the corresponding conversion is complete.
These bits are cleared when the corresponding CDR or LCDR registers are read.
0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished.
1: Corresponding analog channel (if implemented) is enabled and conversion is complete.
Status Register
OVRE6
EOC6
30
22
14
SR
Read-only
0x1C
0x000C0000
–
–
6
OVRE5
EOC5
29
21
13
–
–
5
OVRE4
EOC4
28
20
12
–
–
4
RXBUFF
OVRE3
EOC3
27
19
11
–
3
ENDRX
OVRE2
EOC2
26
18
10
–
2
GOVRE
OVRE1
EOC1
25
17
–
9
1
AT32UC3B
OVRE0
DRDY
EOC0
24
16
–
8
0
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