AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet - Page 246

• Manufacturer Part Number: AT32UC3B0256-Z2UT
• Description: IC MCU AVR32 256KB FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-Z2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64QFN EP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.14.1
Name:
Access:
Offset:
Reset Value: 0x00000000
• SWRST: Software Reset
• SVDIS: TWI Slave Mode Disabled
• SVEN: TWI Slave Mode Enabled
• MSDIS: TWI Master Mode Disabled
• MSEN: TWI Master Mode Enabled
• STOP: Send a STOP Condition
• START: Send a START Condition
32059K–03/2011
SWRST
31
23
15
–
–
–
7
0 = No effect.
1 = Equivalent to a system reset.
0 = No effect.
1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation.
In write operation, the character being transferred must be completely received before disabling.
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Switching from Master to Slave mode is only permitted when TXCOMP = 1.
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are
transmitted in case of write operation. In read operation, the character being transferred must be completely received before
disabling.
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Switching from Slave to Master mode is only permitted when TXCOMP = 1.
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
- In single data byte master read, the START and STOP must both be set.
- In multiple data bytes master read, the STOP must be set after the last data received but one.
- In master read mode, if a NACK bit is received, the STOP is automatically performed.
- In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.
Control Register
CR
Write-only
0x00
30
22
14
–
–
–
6
–
SVDIS
29
21
13
–
–
–
5
SVEN
28
20
12
–
–
–
4
MSDIS
27
19
11
–
–
–
3
MSEN
26
18
10
–
–
–
2
STOP
25
17
–
–
9
–
1
AT32UC3B
START
24
16
–
–
8
–
0
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