ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 125
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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12.5
12.6
12.6.1
8077H–AVR–12/09
Interrupt level
Interrupt priority
Static priority
rupt execution response time is increased by five clock cycles. In addition the response time is
increased by the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,
the program counter is popped from the stack and the stack pointer is incremented.
The interrupt level is independently selected for each interrupt source. For any interrupt request,
the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre-
sponding bit values for the interrupt level configuration of all interrupts is shown in
Table 12-1.
The interrupt level of an interrupt request is compared against the current level and status of the
interrupt controller. An interrupt request on higher level will interrupt any ongoing interrupt han-
dler from a lower level interrupt. When returning from the higher level interrupt handler, the
execution of the lower level interrupt handler will continue.
Within each interrupt level, all interrupts have a priority. When several interrupt requests are
pending, the order of which interrupts are acknowledged is decided both by the level and the pri-
ority of the interrupt request. Interrupts can be organized in a static or dynamic (round-robin)
priority scheme. High and Medium level interrupts and the NMI will always have static priority.
For Low level interrupts, static or dynamic priority scheduling can be selected.
Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector
address decides the priority within one interrupt level where the lowest interrupt vector address
has the highest priority. Refer to the device data sheet for interrupt vector table with the base
address for all modules and peripherals with interrupt. Refer to the interrupt vector summary of
each module and peripheral in this manual for a list of interrupts and their corresponding offset
address within the different modules and peripherals.
Interrupt level
configuration
00
01
10
11
Interrupt level
Group Configuration
MED
OFF
LO
HI
Description
Interrupt disabled.
Low level interrupt
Medium level interrupt
High level interrupt
XMEGA A
Table
12-1.
125
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