ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 305
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8077H–AVR–12/09
Table 25-5.
• Bits 2:0 - EVACT[2:0]: ADC Event Mode
These bits define how many of the selected event channel that are in use, and also some spe-
cial event modes as defined in
sweep triggered by a single event, or an event re-synchronized conversion to achieve a very
accurate timing for the conversion.
Table 25-6.
EVACT[2:0]
EVSEL[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
ADC Event Line Select
ADC Event Mode Select
Group Configuration
SYNCSWEEP
CH0123
SWEEP
CH012
NONE
CH01
CH0
Group Configuration
Table 25-5 on page
0123
1234
2345
3456
4567
567
67
7
Event input operation mode
No event inputs
Event channel with the lowest number, defined by EVSEL
triggers conversion on channel 0
Event channel with the two lowest numbers, defined by
EVSEL trigger conversion on channel 0 and 1 respectively
Event channel with the three lowest numbers, defined by
EVSEL trigger conversion on channel 0, 1 and 2 respectively
Event channel defined by EVSEL trigger conversion on
channel 0, 1, 2 and 3 respectively
One sweep of all active ADC channels defined by SWEEP on
incoming event channel with the lowest number, defined by
EVSEL
One sweep of all active ADC channels defined by SWEEP on
incoming event channel with the lowest number, defined by
EVSEL. In addition, the conversion will be synchronized on
event to ensure a very accurate timing for the conversion.
Reserved
Selected event lines
Event channel 0, 1, 2, 3 as selected inputs
Event channel 1, 2, 3, 4 as selected inputs
Event channel 2, 3, 4, 5 as selected inputs
Event channel 3, 4, 5, 6 as selected inputs
Event channel 4, 5, 6, 7 as selected inputs
Event channel 5, 6, 7 as selected inputs (Max 3
event inputs in use)
Event channel 6, 7 as selected inputs (Max 2 event
inputs in use)
Event channel 7 as selected input (Max 1 event
input in use)
305. This is for instance a complete channel
XMEGA A
305
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