ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 62

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.14.9
5.14.10
5.14.11
5.14.12
8077H–AVR–12/09
SRCADDR1 - DMA Channel Source Address 1
SRCADDR0 - DMA Channel Source Address 0
DESTADDR2 - DMA Channel Destination Address 2
DESTADDR1 - DMA Channel Destination Address 1
• Bit 7:0 - SRCADDR[23:16]: DMA Channel Source Address 2
These bits hold byte 2 of the 24-bits source address.
• Bit 7:0 - SRCADDR[15:8]: DMA Channel Source Address 1
These bits hold byte 1 of the 24-bits source address.
• Bit 7:0 - SRCADDR[7:0]: DMA Channel Source Address 0
These bits hold byte 0 of the 24-bits source address.
DESTADDR0, DESTADDR1 and DESTADDR2 represents the 24-bit value DESTADDR, which
is the DMA channel destination address. DESTADDR2 holds the most significant byte in the reg-
ister. DESTADDR may be automatically incremented or decremented based on settings in the
DESTDIR bits in
Reading and writing 24-bit values require special attention, for details refer to
”Accessing 24- and 32-bit Registers” on page
• Bit 7:0 - DESTADDR[23:16]: DMA Channel Destination Address 2
These bits hold byte 2 of the 24-bits source address.
Bit
+0x08
Read/Write
Initial Value
Bit
+0x0E
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
Bit
+0x0D
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
”ADDRCTRL - DMA Channel Address Control Register” on page
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
DESTADDR[23:16]
R/W
R/W
R/W
4
0
DESTADDR[15:8]
SRCADDR[15:8]
4
0
4
0
4
0
SRCADDR[7:0]
12.
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Section 3.11.1
57.
DESTADDR2
DESTADDR1
SRCADDR1
SRCADDR0
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