ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 183
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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15.7.2
15.7.3
8077H–AVR–12/09
FDEMASK - Fault Detect Event Mask Register
FDCTRL - Fault Detection Control Register
• Bit 7:0 - FDEVMASK[7:0]: Fault Detect Event Mask
These bits enables the corresponding event channel as fault condition input source. Event from
all event channels will be ORed together allowing multiple sources to be used for fault detection
at the same time. When a fault is detected the Fault Detect Flag FDF is set and the fault detect
action (FDACT) will be performed.
• Bit 7:5 - RES - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - FDDBD: Fault Detection on Debug Break Detection
By default, when this bit is cleared and the fault protection is enabled, and OCD break request is
treated as a fault. When this bit is set, an OCD break request will not trigger a fault condition.
• Bit 3 - RES - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2- FDMODE: Fault Detection Restart Mode
This bit sets the fault protection restart mode. When this bit is cleared Latched Mode is use, and
when this is set Cycle-by-Cycle Mode is used.
In Latched Mode the waveform output will remain in the fault state until the fault condition is no
longer active and the FDF has been cleared by software. When both of these conditions are
met, the waveform output will return to normal operation at the next UPDATE condition.
In Cycle-by-Cycle Mode the waveform output will remain in the fault state until the fault condition
is no longer active. When this condition is met, the waveform output will return to normal opera-
tion at the next UPDATE condition
• Bit 1:0 - FDACT[1:0]: Fault Detection Action
These bits define the action performed if a fault condition is detected, according to
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
R/W
R
7
0
-
7
0
R/W
R
6
0
-
6
0
R/W
R
5
0
-
5
0
.
FDDBD
R/W
R/W
4
0
FDEVMASK[7:0]
4
0
R/W
R
3
0
-
3
0
FDMODE
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
FDACT[1:0]
XMEGA A
R/W
R/W
0
0
0
0
Table
FDEMASK
FDCTRL
15-1.
183
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