ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 164
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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14.10 DMA Support.
14.11 Timer/Counter Commands
8077H–AVR–12/09
The interrupt flags can be used to trigger DMA transactions.
transfer triggers available from the T/C, and the DMA action that will clear the transfer trigger.
For more details on using DMA refer to
Table 14-2.
A set of commands can be given to the Timer/Counter by software to immediately change the
state of the module. These commands give direct control of the Update, Restart, and Reset
signals.
An update command has the same effect as when an update condition occurs. The update com-
mand is ignored if the Lock Update bit is set.
The software can force a restart of the current waveform period by issuing a restart command. In
this case the Counter, direction, and all compare outputs are set to zero.
A reset command will set all Timer/Counter registers to their initial values. A reset can only be
given when the Timer/Counter is not running (OFF).
Request
OV/UNFIF
ERRIF
CCxIF
DMA Request Sources
Acknowledge
DMA Controller writes to CNT
DMA Controller writes to PER
DMA Controller writes to PERBUF
N/A
DMA Controller access of CCx
DMA Controller access of CCxBUF
”DMA - Direct Memory Access Controller” on page
Table 14-2 on page 164
Comment
Input Capture operation
Output Compare operation
XMEGA A
lists the
49.
164
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