ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 111

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7DALIF2
Note:
SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the
SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See
(OVR) on page
bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is pulled low in master mode (see
fault (MODF) on page
register. This bit is cleared by a software sequence (An access to the SPICSR register while
MODF=1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it disables the alternate function of the SPI
output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it disables the alternate function of the SPI
SS pin and uses the SSI bit value instead. See
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free for
general-purpose I/O)
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the
SS slave select signal when the SSM bit is set.
0: Slave selected
106). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR
105). An SPI interrupt can be generated if SPIE=1 in the SPICR
Device
and an external device has been completed.
Section 17.4.1: Slave select
Figure
Serial peripheral interface (SPI)
50).
Overrun condition
management.
Master mode
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