ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 44

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Supply, reset and clock management
9.7.4
Note:
44/171
Register description
System integrity (SI) control/status register (SICSR)
Read/Write
Reset Value: 0000 0xx0 (0xh)
Bit 7:5 = Reserved, must be kept cleared.
Bit 4 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given by the following
table.
Table 14.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set automatically when the PLL reaches its
operating frequency.
0: PLL not locked
1: PLL locked
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware
(LVD reset) and cleared by software (by reading). When the LVD is disabled by OPTION
BYTE, the LVDRF bit value is undefined.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request
is generated when the AVDF bit is set. Refer to
supply on page 42
0: V
1: V
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when software
enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
External RESET pin
Watchdog
LVD
7
0
DD
DD
over AVD threshold
under AVD threshold
0
Reset flags
for additional details.
RESET sources
0
WDGRF
LOCKED
Figure 18
and to
LVDRF
LVDRF
0
0
1
Monitoring the VDD main
AVDF
WDGRF
ST7DALIF2
X
0
1
AVDIE
0