ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 23

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7DALIF2
7
7.1
7.2
7.3
Data EEPROM
Introduction
The Electrically Erasable Programmable Read Only Memory can be used as a non volatile
back-up for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
Main features
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■
■
■
■
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Figure 5.
Memory access
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in
different memory access modes.
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
EECSR
Up to 32 Bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle duration
Wait mode management
Readout protection
EEPROM block diagram
0
ADDRESS BUS
0
DECODER
ADDRESS
0
0
4
0
DECODER
0
4
4
ROW
E2LAT
E2PGM
128
MULTIPLEXER
DATA
(1 ROW = 32 x 8 BITS)
MEMORY MATRIX
HIGH VOLTAGE
Figure 6
DATA BUS
EEPROM
PUMP
DATA LATCHES
128
32 x 8 BITS
describes these
Data EEPROM
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