ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 117

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7DALIF2
18.7.2
18.7.3
Note:
Table 51.
1.
Data register high (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
AMP control/data register low (ADCDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. User is suggested to use this bit to calibrate the ADC
when amplifier is ON. Setting this bit internally connects amplifier input to 0 V. Hence,
corresponding ADC output can be used in software to eliminate amplifier-offset error.
0: Calibration off
1: Calibration on (The input voltage of the amp is set to 0V)
It is advised to use this bit to calibrate the ADC when the amplifier is ON. Setting this bit
internally connects the amplifier input to 0v. Hence, the corresponding ADC output can be
used in software to eliminate an amplifier-offset error.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used together with the SPEED bit to configure
the ADC clock speed as shown on the table below.
Table 52.
The number of channels is device dependent. Refer to
D9
7
7
0
Channel selection bits (continued)
ADC clock speed selection
D8
0
Channel pin
AIN3
AIN4
AIN5
AIN6
D7
0
f
f
f
CPU
CPU
f
ADC
CPU
(1)
/2
/4
AMP CAL
D6
Section 4: Pin description on page
SLOW
D5
CH2
AMPSEL
0
1
1
1
D4
10-bit A/D converter (ADC)
13.
SLOW
0
0
1
CH1
1
0
0
1
D3
D1
SPEED
CH0
0
1
x
117/171
1
0
1
0
D2
D0
0
0