ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 79

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7DALIF2
14.6.4
14.6.5
14.6.6
14.6.7
software should read the counter value in two consecutive read operations. The CNTRH
register can be incremented between the two reads, and in order to be accurate when
f
If CNTRL is close to its highest value, CNTRH could be incremented before it is read
When a counter overflow occurs, the counter restarts from the value specified in the ATR
register.
Autoreload register (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
Autoreload register (ATRL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by software. The ATR register value is automatically
loaded into the upcounter when an overflow occurs. The register value is used to set the
PWM frequency.
PWM output control register (PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = OE[3:0] PWMx output enable.
These bits are set and cleared by software and cleared by hardware after a reset.
0: PWM mode disabled. PWMx output alternate function disabled: I/O pin free for general
purpose I/O after an overflow event.
1: PWM mode enabled
PWMx control status register (PWMxCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2= Reserved, must be kept cleared.
TIMER
ATR7
15
0
7
7
0
7
0
=f
CPU
, the software should take this into account when CNTRL and CNTRH are read.
ATR6
OE3
0
6
0
ATR5
0
0
0
ATR4
OE2
0
0
ATR11
ATR3
0
0
12-bit autoreload timer 2 (AT2)
ATR10
ATR2
OE1
0
ATR9
ATR1
OPx
0
CMPFx
ATR0
ATR8
OE0
0
0
8
0
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