ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 98

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DALI communication module
16.11.6
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1: Acknowledge
Bit 1 = RTS Receive/Transmit state.
This bit is set/cleared by software and cleared by hardware after a reset.
This bit must be set to ’1’ after a forward frame is received, if a backward frame is required.
This bit must be cleared after a backward frame is transmitted, if a forward frame is required.
0: The DCM is set to Receive state
1: The DCM is set to Transmit state
Bit 0 = FTS Force Transmit state.
This bit is set/cleared by software and cleared by hardware after a reset.
When this bit is set, the DCM is forced into Transmit state. Preferably before forcing the
DCM into Transmit state, the user should reset and set the DCME bit in the DCMCR
register. An interrupt flag
(ITF) is generated after a forced transmission.
0: The DCM is not forced to Transmit state
1: The DCM is forced to Transmit state
DCM control/status register (DCMCSR)
Read only (except for bit 7)
Reset Value: 0000 0000 (00h)
Bit 7 = ITE Interrupt Enable.
This bit is set/cleared by software and cleared by hardware after a reset.
When set, this bit allows the generation of DALI interrupts.
0: DCM interrupt (ITF) disabled
1: DCM interrupt (ITF) enabled
Bit 6 = ITF Interrupt Flag. (Read only)
This bit is set/cleared by hardware and read by software.
This bit is set after the end of the "backward frame" transmission or the "forward frame"
reception. It is cleared by setting the RTA bit in the DCMCR register. It is set after a forced
transmission (see the FTS bit).
0: Not the end of reception/transmission
1: End of reception/transmission
Bit 5 = EF Error Flag. (Read only)
This bit is set/cleared by hardware. It is cleared by reading the DCMCSR register.
This bit is set when either the DALI data format received is wrong or an interface failure is
detected.
0: No data format error during reception
1: Data format error during reception
Bit 4 = RTF Receive/Transmit Flag. (Read only)
This bit is set/reset by hardware and read by software.
ITE
7
ITF
EF
RTF
CK3
CK2
CK1
ST7DALIF2
CK0
0