ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 53

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7DALIF2
Figure 23. Halt mode timing overview
Figure 24. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
5. If the PLL is enabled by option byte, it outputs the clock after a delay of t
Table 15: Interrupt mapping
during the interrupt routine and cleared when the CC register is popped.
[Active Halt disabled]
INSTRUCTION
RUN
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
HALT
(Active-halt disabled)
N
WATCHDOG
for more details.
WDGHALT
RESET
HALT
1
INTERRUPT
Y
1)
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
RESET
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BIT
OR
N
CYCLE
RESET
Y
WATCHDOG
DELAY
VECTOR
FETCH
DISABLE
2)
OFF
OFF
OFF
OFF
ON
ON
X
5)
ON
ON
ON
X
RUN
0
4)
4)
STARTUP
(see
Power saving modes
Figure
11).
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