ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 66

IC MCU 8BIT 8K FLASH 20-SOIC

ST7FDALIF2M6TR

Manufacturer Part Number
ST7FDALIF2M6TR
Description
IC MCU 8BIT 8K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FDALIF2M6TR

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
DALI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7DALI
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
DALI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel / 13 bit, 7 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FDALIF2M6TR
Manufacturer:
NEC
Quantity:
670
I/O ports
12.3
12.4
12.5
12.6
66/171
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific I/O port features such as ADC input or open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in
Other transitions are potentially risky and should be avoided, since they may present
unwanted side-effects such as spurious interrupt generation.
Figure 31. Interrupt I/O port state transitions
Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to
Low power modes
Table 27.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 28.
External interrupt on selected
external event
Mode
Wait
Halt
Interrupt event
Effect of low power modes on I/O ports
I/O port interrupt control/wake-up capability
floating/pull-up
No effect on I/O ports. External interrupts cause the device to exit from Wait
mode.
No effect on I/O ports. External interrupts cause the device to exit from Halt
mode.
interrupt
INPUT
01
(reset state)
floating
INPUT
00
Event
flag
-
open-drain
OUTPUT
10
Description
XX
control
Enable
DDRx
ORx
= DDR, OR
bit
OUTPUT
push-pull
11
Section
from
Wait
Exit
Yes
20.
ST7DALIF2
Figure
from
Halt
Exit
Yes
31.

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