S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 157

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S9S12P64J0MFT

Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12P64J0MFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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S9S12P64J0MFT
0
6.1.4
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
6.1.5
6.2
There are no external signals associated with this module.
Freescale Semiconductor
Enable
BDM
x
0
0
1
1
TAGHITS
SECURE
CPU BUS
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Modes of Operation
Block Diagram
Active
BDM
0
1
0
1
x
Secure
MCU
1
0
0
0
0
Table 6-2. Mode Dependent Restriction Summary
COMPARATOR A
COMPARATOR C
COMPARATOR B
Figure 6-1. Debug Module Block Diagram
S12P-Family Reference Manual, Rev. 1.13
Matches Enabled
Comparator
Yes
Yes
Yes
No
MATCH1
MATCH2
MATCH0
Active BDM not possible when not enabled
Breakpoints
Only SWI
Possible
Yes
Yes
No
CONTROL
MATCH
LOGIC
TAG &
TRANSITION
STATE
BREAKPOINT REQUESTS
Possible
Tagging
S12S Debug Module (S12SDBGV2)
Yes
Yes
Yes
No
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
Possible
Tracing
Yes
Yes
No
No
157

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