S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 44
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Device Overview MC9S12P-Family
1.9.2
The MC9S12P has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description
refer to S12CPMU section.
1.10
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 13.5 Security
1.11
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1
Table 1-11. lists all Reset sources and the vector locations. Resets are explained in detail in the Section
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU)
1.11.2
Table 1-12
Section Chapter 4 Interrupt Module (S12SINTV1)) provides an interrupt vector base register (IVBR)
to relocate the vectors.
44
Vector Address
Vector base + $F8
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector Address
Security
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Low Power Operation
Resets
Interrupt Vectors
$FFFC
$FFFE
$FFFE
$FFFE
$FFFE
$FFFA
(1)
Unimplemented instruction trap
Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
Interrupt Source
Table 1-11. Reset Sources and Vector Locations
XIRQ
SWI
IRQ
Low Voltage Reset (LVR)
S12P-Family Reference Manual, Rev. 1.13
Power-On Reset (POR)
Illegal Address Reset
COP watchdog reset
External pin RESET
Clock monitor reset
Reset Source
Mask
None
None
CCR
X Bit
I bit
Mask
None
None
None
None
None
None
IRQCR (IRQEN)
CCR
Local Enable
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Local Enable
None
None
None
None
Freescale Semiconductor
from STOP
Wake up
Yes
Yes
-
-
from WAIT
Wakeup
Yes
Yes
-
-
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