S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 343
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Read: always read 0x0000 in normal modes
Write: unimplemented in normal modes
10.3.2.8
This register is reserved for factory testing of the PWM module and is not available in normal modes.
Read: always read 0x0000 in normal modes
Write: unimplemented in normal modes
10.3.2.9
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is
generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.
Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).
Freescale Semiconductor
Module Base + 0x0007
Module Base + 0x0008
Reset
Reset
W
W
R
R
Clock SA = Clock A / (2 * PWMSCLA)
Bit 7
Reserved Register (PWMPRSC)
PWM Scale A Register (PWMSCLA)
0
0
0
7
7
Writing to this register when in special modes can alter the PWM
functionality.
Writing to this register when in special modes can alter the PWM
functionality.
When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale
value of 256. Clock A is thus divided by 512.
= Unimplemented or Reserved
0
0
0
6
6
6
Figure 10-11. PWM Scale A Register (PWMSCLA)
Figure 10-10. Reserved Register (PWMPRSC)
S12P-Family Reference Manual, Rev. 1.13
0
0
0
5
5
5
NOTE
NOTE
NOTE
0
0
0
4
4
4
Pulse-Width Modulator (PWM8B6CV1) Block Description
0
0
0
3
3
3
0
0
0
2
2
2
0
0
0
1
1
1
Bit 0
0
0
0
0
0
343
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